2 * armboot - Startup Code for XScale CPU-core
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
19 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm-offsets.h>
28 #ifdef CONFIG_SPL_BUILD
45 .word 0x12345678 /* now 16*4=64 */
47 ldr pc, _undefined_instruction
48 ldr pc, _software_interrupt
49 ldr pc, _prefetch_abort
55 _undefined_instruction: .word undefined_instruction
56 _software_interrupt: .word software_interrupt
57 _prefetch_abort: .word prefetch_abort
58 _data_abort: .word data_abort
59 _not_used: .word not_used
62 _pad: .word 0x12345678 /* now 16*4=64 */
63 #endif /* CONFIG_SPL_BUILD */
65 .balignl 16,0xdeadbeef
67 *************************************************************************
69 * Startup Code (reset vector)
71 * do important init only if we don't start from memory!
72 * setup Memory and board specific bits prior to relocation.
73 * relocate armboot to ram
76 *************************************************************************
80 /* IRQ stack memory (calculated at run-time) */
81 .globl IRQ_STACK_START
85 /* IRQ stack memory (calculated at run-time) */
86 .globl FIQ_STACK_START
91 /* IRQ stack memory (calculated at run-time) + 8 bytes */
92 .globl IRQ_STACK_START_IN
97 * the actual reset code
102 * set the cpu to SVC32 mode
109 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
113 #ifdef CONFIG_CPU_PXA25X
114 bl lock_cache_for_stack
119 /*------------------------------------------------------------------------------*/
121 .globl c_runtime_cpu_setup
124 #ifdef CONFIG_CPU_PXA25X
126 * Unlock (actually, disable) the cache now that board_init_f
127 * is done. We could do this earlier but we would need to add
128 * a new C runtime hook, whereas c_runtime_cpu_setup already
130 * As this routine is just a call to cpu_init_crit, let us
131 * tail-optimize and do a simple branch here.
139 *************************************************************************
141 * CPU_init_critical registers
143 * setup important registers
144 * setup memory timing
146 *************************************************************************
148 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
151 * flush v4 I/D caches
154 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
155 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
158 * disable MMU stuff and caches
160 mrc p15, 0, r0, c1, c0, 0
161 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
162 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
163 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
164 mcr p15, 0, r0, c1, c0, 0
166 mov pc, lr /* back to my caller */
167 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
169 #ifndef CONFIG_SPL_BUILD
171 *************************************************************************
175 *************************************************************************
180 #define S_FRAME_SIZE 72
202 #define MODE_SVC 0x13
206 * use bad_save_user_regs for abort/prefetch/undef/swi ...
207 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
210 .macro bad_save_user_regs
211 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
212 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
214 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
215 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
216 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
220 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
221 mov r0, sp @ save current stack into r0 (param register)
224 .macro irq_save_user_regs
225 sub sp, sp, #S_FRAME_SIZE
226 stmia sp, {r0 - r12} @ Calling r0-r12
227 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
228 stmdb r8, {sp, lr}^ @ Calling SP, LR
229 str lr, [r8, #0] @ Save calling PC
231 str r6, [r8, #4] @ Save CPSR
232 str r0, [r8, #8] @ Save OLD_R0
236 .macro irq_restore_user_regs
237 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
239 ldr lr, [sp, #S_PC] @ Get PC
240 add sp, sp, #S_FRAME_SIZE
241 subs pc, lr, #4 @ return & move spsr_svc into cpsr
245 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
247 str lr, [r13] @ save caller lr in position 0 of saved stack
248 mrs lr, spsr @ get the spsr
249 str lr, [r13, #4] @ save spsr in position 1 of saved stack
251 mov r13, #MODE_SVC @ prepare SVC-Mode
253 msr spsr, r13 @ switch modes, make sure moves will execute
254 mov lr, pc @ capture return pc
255 movs pc, lr @ jump to next instruction & switch modes.
258 .macro get_bad_stack_swi
259 sub r13, r13, #4 @ space on current stack for scratch reg.
260 str r0, [r13] @ save R0's value.
261 ldr r0, IRQ_STACK_START_IN @ get data regions start
262 str lr, [r0] @ save caller lr in position 0 of saved stack
263 mrs lr, spsr @ get the spsr
264 str lr, [r0, #4] @ save spsr in position 1 of saved stack
265 ldr lr, [r0] @ restore lr
266 ldr r0, [r13] @ restore r0
267 add r13, r13, #4 @ pop stack entry
270 .macro get_irq_stack @ setup IRQ stack
271 ldr sp, IRQ_STACK_START
274 .macro get_fiq_stack @ setup FIQ stack
275 ldr sp, FIQ_STACK_START
277 #endif /* CONFIG_SPL_BUILD */
282 #ifdef CONFIG_SPL_BUILD
285 bl hang /* hang and never return */
286 #else /* !CONFIG_SPL_BUILD */
288 undefined_instruction:
291 bl do_undefined_instruction
297 bl do_software_interrupt
317 #ifdef CONFIG_USE_IRQ
324 irq_restore_user_regs
329 /* someone ought to write a more effiction fiq_save_user_regs */
332 irq_restore_user_regs
350 #endif /* CONFIG_SPL_BUILD */
354 * Enable MMU to use DCache as DRAM.
356 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
357 * other possible memory available to hold stack.
359 #ifdef CONFIG_CPU_PXA25X
361 mrc p15, 0, \reg, c2, c0, 0
365 lock_cache_for_stack:
366 /* Domain access -- enable for all CPs */
368 mcr p15, 0, r0, c3, c0, 0
370 /* Point TTBR to MMU table */
372 mcr p15, 0, r0, c2, c0, 0
374 /* Kick in MMU, ICache, DCache, BTB */
375 mrc p15, 0, r0, c1, c0, 0
380 mcr p15, 0, r0, c1, c0, 0
383 /* Unlock Icache, Dcache */
384 mcr p15, 0, r0, c9, c1, 1
385 mcr p15, 0, r0, c9, c2, 1
387 /* Flush Icache, Dcache, BTB */
388 mcr p15, 0, r0, c7, c7, 0
390 /* Unlock I-TLB, D-TLB */
391 mcr p15, 0, r0, c10, c4, 1
392 mcr p15, 0, r0, c10, c8, 1
395 mcr p15, 0, r0, c8, c7, 0
397 /* Allocate 4096 bytes of Dcache as RAM */
399 /* Drain pending loads and stores */
400 mcr p15, 0, r0, c7, c10, 4
405 mcr p15, 0, r0, c9, c2, 0
408 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
413 mcr p15, 0, r1, c7, c2, 5
414 /* Drain pending loads and stores */
415 mcr p15, 0, r0, c7, c10, 4
422 /* Drain pending loads and stores */
423 mcr p15, 0, r0, c7, c10, 4
425 mcr p15, 0, r2, c9, c2, 0
430 .section .mmutable, "a"
433 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
436 .word (__base << 20) | 0xc12
437 .set __base, __base + 1
440 /* 0xfff00000 : 1:1, cached mapping */
441 .word (0xfff << 20) | 0x1c1e
442 #endif /* CONFIG_CPU_PXA25X */