2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
19 /* return 1 if a pin_pupd_is in range */
20 #define pmux_pin_pupd_isvalid(pupd) \
21 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
23 /* return 1 if a pin_tristate_is in range */
24 #define pmux_pin_tristate_isvalid(tristate) \
25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
27 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
28 /* return 1 if a pin_io_is in range */
29 #define pmux_pin_io_isvalid(io) \
30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
32 /* return 1 if a pin_lock is in range */
33 #define pmux_pin_lock_isvalid(lock) \
34 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
36 /* return 1 if a pin_od is in range */
37 #define pmux_pin_od_isvalid(od) \
38 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
40 /* return 1 if a pin_ioreset_is in range */
41 #define pmux_pin_ioreset_isvalid(ioreset) \
42 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
43 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
45 #ifdef TEGRA_PMX_HAS_RCV_SEL
46 /* return 1 if a pin_rcv_sel_is in range */
47 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
48 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
49 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
50 #endif /* TEGRA_PMX_HAS_RCV_SEL */
51 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
53 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
55 #if defined(CONFIG_TEGRA20)
57 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
58 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
60 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
61 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
63 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
64 #define TRI_SHIFT(grp) ((grp) % 32)
68 #define REG(pin) _R(0x3000 + ((pin) * 4))
70 #define MUX_REG(pin) REG(pin)
71 #define MUX_SHIFT(pin) 0
73 #define PULL_REG(pin) REG(pin)
74 #define PULL_SHIFT(pin) 2
76 #define TRI_REG(pin) REG(pin)
77 #define TRI_SHIFT(pin) 4
79 #endif /* CONFIG_TEGRA20 */
81 #define DRV_REG(group) _R(0x868 + ((group) * 4))
86 #define IO_RESET_SHIFT 8
87 #define RCV_SEL_SHIFT 9
89 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
91 u32 *reg = MUX_REG(pin);
95 if (func == PMUX_FUNC_DEFAULT)
98 /* Error check on pin and func */
99 assert(pmux_pingrp_isvalid(pin));
100 assert(pmux_func_isvalid(func));
102 if (func >= PMUX_FUNC_RSVD1) {
103 mux = (func - PMUX_FUNC_RSVD1) & 3;
105 /* Search for the appropriate function */
106 for (i = 0; i < 4; i++) {
107 if (tegra_soc_pingroups[pin].funcs[i] == func) {
116 val &= ~(3 << MUX_SHIFT(pin));
117 val |= (mux << MUX_SHIFT(pin));
121 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
123 u32 *reg = PULL_REG(pin);
126 /* Error check on pin and pupd */
127 assert(pmux_pingrp_isvalid(pin));
128 assert(pmux_pin_pupd_isvalid(pupd));
131 val &= ~(3 << PULL_SHIFT(pin));
132 val |= (pupd << PULL_SHIFT(pin));
136 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
138 u32 *reg = TRI_REG(pin);
141 /* Error check on pin */
142 assert(pmux_pingrp_isvalid(pin));
143 assert(pmux_pin_tristate_isvalid(tri));
146 if (tri == PMUX_TRI_TRISTATE)
147 val |= (1 << TRI_SHIFT(pin));
149 val &= ~(1 << TRI_SHIFT(pin));
153 void pinmux_tristate_enable(enum pmux_pingrp pin)
155 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
158 void pinmux_tristate_disable(enum pmux_pingrp pin)
160 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
163 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
164 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
169 if (io == PMUX_PIN_NONE)
172 /* Error check on pin and io */
173 assert(pmux_pingrp_isvalid(pin));
174 assert(pmux_pin_io_isvalid(io));
177 if (io == PMUX_PIN_INPUT)
178 val |= (io & 1) << IO_SHIFT;
180 val &= ~(1 << IO_SHIFT);
184 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
189 if (lock == PMUX_PIN_LOCK_DEFAULT)
192 /* Error check on pin and lock */
193 assert(pmux_pingrp_isvalid(pin));
194 assert(pmux_pin_lock_isvalid(lock));
197 if (lock == PMUX_PIN_LOCK_ENABLE) {
198 val |= (1 << LOCK_SHIFT);
200 if (val & (1 << LOCK_SHIFT))
201 printf("%s: Cannot clear LOCK bit!\n", __func__);
202 val &= ~(1 << LOCK_SHIFT);
209 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
214 if (od == PMUX_PIN_OD_DEFAULT)
217 /* Error check on pin and od */
218 assert(pmux_pingrp_isvalid(pin));
219 assert(pmux_pin_od_isvalid(od));
222 if (od == PMUX_PIN_OD_ENABLE)
223 val |= (1 << OD_SHIFT);
225 val &= ~(1 << OD_SHIFT);
231 static void pinmux_set_ioreset(enum pmux_pingrp pin,
232 enum pmux_pin_ioreset ioreset)
237 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
240 /* Error check on pin and ioreset */
241 assert(pmux_pingrp_isvalid(pin));
242 assert(pmux_pin_ioreset_isvalid(ioreset));
245 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
246 val |= (1 << IO_RESET_SHIFT);
248 val &= ~(1 << IO_RESET_SHIFT);
254 #ifdef TEGRA_PMX_HAS_RCV_SEL
255 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
256 enum pmux_pin_rcv_sel rcv_sel)
261 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
264 /* Error check on pin and rcv_sel */
265 assert(pmux_pingrp_isvalid(pin));
266 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
269 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
270 val |= (1 << RCV_SEL_SHIFT);
272 val &= ~(1 << RCV_SEL_SHIFT);
277 #endif /* TEGRA_PMX_HAS_RCV_SEL */
278 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
280 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
282 enum pmux_pingrp pin = config->pingrp;
284 pinmux_set_func(pin, config->func);
285 pinmux_set_pullupdown(pin, config->pull);
286 pinmux_set_tristate(pin, config->tristate);
287 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
288 pinmux_set_io(pin, config->io);
289 pinmux_set_lock(pin, config->lock);
290 pinmux_set_od(pin, config->od);
291 pinmux_set_ioreset(pin, config->ioreset);
292 #ifdef TEGRA_PMX_HAS_RCV_SEL
293 pinmux_set_rcv_sel(pin, config->rcv_sel);
298 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
303 for (i = 0; i < len; i++)
304 pinmux_config_pingrp(&config[i]);
307 #ifdef TEGRA_PMX_HAS_DRVGRPS
309 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
311 #define pmux_slw_isvalid(slw) \
312 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
314 #define pmux_drv_isvalid(drv) \
315 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
317 #define pmux_lpmd_isvalid(lpm) \
318 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
320 #define pmux_schmt_isvalid(schmt) \
321 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
323 #define pmux_hsm_isvalid(hsm) \
324 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
327 #define SCHMT_SHIFT 3
329 #define LPMD_MASK (3 << LPMD_SHIFT)
330 #define DRVDN_SHIFT 12
331 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
332 #define DRVUP_SHIFT 20
333 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
334 #define SLWR_SHIFT 28
335 #define SLWR_MASK (3 << SLWR_SHIFT)
336 #define SLWF_SHIFT 30
337 #define SLWF_MASK (3 << SLWF_SHIFT)
339 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
341 u32 *reg = DRV_REG(grp);
344 /* NONE means unspecified/do not change/use POR value */
345 if (slwf == PMUX_SLWF_NONE)
348 /* Error check on pad and slwf */
349 assert(pmux_drvgrp_isvalid(grp));
350 assert(pmux_slw_isvalid(slwf));
354 val |= (slwf << SLWF_SHIFT);
360 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
362 u32 *reg = DRV_REG(grp);
365 /* NONE means unspecified/do not change/use POR value */
366 if (slwr == PMUX_SLWR_NONE)
369 /* Error check on pad and slwr */
370 assert(pmux_drvgrp_isvalid(grp));
371 assert(pmux_slw_isvalid(slwr));
375 val |= (slwr << SLWR_SHIFT);
381 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
383 u32 *reg = DRV_REG(grp);
386 /* NONE means unspecified/do not change/use POR value */
387 if (drvup == PMUX_DRVUP_NONE)
390 /* Error check on pad and drvup */
391 assert(pmux_drvgrp_isvalid(grp));
392 assert(pmux_drv_isvalid(drvup));
396 val |= (drvup << DRVUP_SHIFT);
402 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
404 u32 *reg = DRV_REG(grp);
407 /* NONE means unspecified/do not change/use POR value */
408 if (drvdn == PMUX_DRVDN_NONE)
411 /* Error check on pad and drvdn */
412 assert(pmux_drvgrp_isvalid(grp));
413 assert(pmux_drv_isvalid(drvdn));
417 val |= (drvdn << DRVDN_SHIFT);
423 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
425 u32 *reg = DRV_REG(grp);
428 /* NONE means unspecified/do not change/use POR value */
429 if (lpmd == PMUX_LPMD_NONE)
432 /* Error check pad and lpmd value */
433 assert(pmux_drvgrp_isvalid(grp));
434 assert(pmux_lpmd_isvalid(lpmd));
438 val |= (lpmd << LPMD_SHIFT);
444 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
446 u32 *reg = DRV_REG(grp);
449 /* NONE means unspecified/do not change/use POR value */
450 if (schmt == PMUX_SCHMT_NONE)
453 /* Error check pad */
454 assert(pmux_drvgrp_isvalid(grp));
455 assert(pmux_schmt_isvalid(schmt));
458 if (schmt == PMUX_SCHMT_ENABLE)
459 val |= (1 << SCHMT_SHIFT);
461 val &= ~(1 << SCHMT_SHIFT);
467 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
469 u32 *reg = DRV_REG(grp);
472 /* NONE means unspecified/do not change/use POR value */
473 if (hsm == PMUX_HSM_NONE)
476 /* Error check pad */
477 assert(pmux_drvgrp_isvalid(grp));
478 assert(pmux_hsm_isvalid(hsm));
481 if (hsm == PMUX_HSM_ENABLE)
482 val |= (1 << HSM_SHIFT);
484 val &= ~(1 << HSM_SHIFT);
490 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
492 enum pmux_drvgrp grp = config->drvgrp;
494 pinmux_set_drvup_slwf(grp, config->slwf);
495 pinmux_set_drvdn_slwr(grp, config->slwr);
496 pinmux_set_drvup(grp, config->drvup);
497 pinmux_set_drvdn(grp, config->drvdn);
498 pinmux_set_lpmd(grp, config->lpmd);
499 pinmux_set_schmt(grp, config->schmt);
500 pinmux_set_hsm(grp, config->hsm);
503 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
508 for (i = 0; i < len; i++)
509 pinmux_config_drvgrp(&config[i]);
511 #endif /* TEGRA_PMX_HAS_DRVGRPS */