Merge branch 'u-boot/master'
[karo-tx-uboot.git] / arch / arm / cpu / tegra124-common / clock.c
1 /*
2  * (C) Copyright 2013
3  * NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /* Tegra124 Clock control functions */
9
10 #include <common.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sysctr.h>
14 #include <asm/arch/tegra.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
17 #include <div64.h>
18 #include <fdtdec.h>
19
20 /*
21  * Clock types that we can use as a source. The Tegra124 has muxes for the
22  * peripheral clocks, and in most cases there are four options for the clock
23  * source. This gives us a clock 'type' and exploits what commonality exists
24  * in the device.
25  *
26  * Letters are obvious, except for T which means CLK_M, and S which means the
27  * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
28  * datasheet) and PLL_M are different things. The former is the basic
29  * clock supplied to the SOC from an external oscillator. The latter is the
30  * memory clock PLL.
31  *
32  * See definitions in clock_id in the header file.
33  */
34 enum clock_type_id {
35         CLOCK_TYPE_AXPT,        /* PLL_A, PLL_X, PLL_P, CLK_M */
36         CLOCK_TYPE_MCPA,        /* and so on */
37         CLOCK_TYPE_MCPT,
38         CLOCK_TYPE_PCM,
39         CLOCK_TYPE_PCMT,
40         CLOCK_TYPE_PDCT,
41         CLOCK_TYPE_ACPT,
42         CLOCK_TYPE_ASPTE,
43         CLOCK_TYPE_PMDACD2T,
44         CLOCK_TYPE_PCST,
45
46         CLOCK_TYPE_PC2CC3M,
47         CLOCK_TYPE_PC2CC3S_T,
48         CLOCK_TYPE_PC2CC3M_T,
49         CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
50         CLOCK_TYPE_MC2CC3P_A,
51         CLOCK_TYPE_M,
52         CLOCK_TYPE_MCPTM2C2C3,
53         CLOCK_TYPE_PC2CC3T_S,
54         CLOCK_TYPE_AC2CC3P_TS2,
55
56         CLOCK_TYPE_COUNT,
57         CLOCK_TYPE_NONE = -1,   /* invalid clock type */
58 };
59
60 enum {
61         CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
62 };
63
64 /*
65  * Clock source mux for each clock type. This just converts our enum into
66  * a list of mux sources for use by the code.
67  *
68  * Note:
69  *  The extra column in each clock source array is used to store the mask
70  *  bits in its register for the source.
71  */
72 #define CLK(x) CLOCK_ID_ ## x
73 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
74         { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
75                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
76                 MASK_BITS_31_30},
77         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
78                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
79                 MASK_BITS_31_30},
80         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
81                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
82                 MASK_BITS_31_30},
83         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
84                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
85                 MASK_BITS_31_30},
86         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
87                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
88                 MASK_BITS_31_30},
89         { CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
90                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
91                 MASK_BITS_31_30},
92         { CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
93                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
94                 MASK_BITS_31_30},
95         { CLK(AUDIO),   CLK(SFROM32KHZ),        CLK(PERIPH),    CLK(OSC),
96                 CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
97                 MASK_BITS_31_29},
98         { CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
99                 CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
100                 MASK_BITS_31_29},
101         { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
102                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
103                 MASK_BITS_31_28},
104
105         /* Additional clock types on Tegra114+ */
106         /* CLOCK_TYPE_PC2CC3M */
107         { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
108                 CLK(MEMORY),    CLK(NONE),      CLK(NONE),      CLK(NONE),
109                 MASK_BITS_31_29},
110         /* CLOCK_TYPE_PC2CC3S_T */
111         { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
112                 CLK(SFROM32KHZ), CLK(NONE),     CLK(OSC),       CLK(NONE),
113                 MASK_BITS_31_29},
114         /* CLOCK_TYPE_PC2CC3M_T */
115         { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
116                 CLK(MEMORY),    CLK(NONE),      CLK(OSC),       CLK(NONE),
117                 MASK_BITS_31_29},
118         /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
119         { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
120                 CLK(MEMORY),    CLK(NONE),      CLK(OSC),       CLK(NONE),
121                 MASK_BITS_31_29},
122         /* CLOCK_TYPE_MC2CC3P_A */
123         { CLK(MEMORY),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
124                 CLK(PERIPH),    CLK(NONE),      CLK(AUDIO),     CLK(NONE),
125                 MASK_BITS_31_29},
126         /* CLOCK_TYPE_M */
127         { CLK(MEMORY),          CLK(NONE),      CLK(NONE),      CLK(NONE),
128                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
129                 MASK_BITS_31_30},
130         /* CLOCK_TYPE_MCPTM2C2C3 */
131         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
132                 CLK(MEMORY2),   CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
133                 MASK_BITS_31_29},
134         /* CLOCK_TYPE_PC2CC3T_S */
135         { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
136                 CLK(OSC),       CLK(NONE),      CLK(SFROM32KHZ), CLK(NONE),
137                 MASK_BITS_31_29},
138         /* CLOCK_TYPE_AC2CC3P_TS2 */
139         { CLK(AUDIO),   CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
140                 CLK(PERIPH),    CLK(NONE),      CLK(OSC),       CLK(SRC2),
141                 MASK_BITS_31_29},
142 };
143
144 /*
145  * Clock type for each peripheral clock source. We put the name in each
146  * record just so it is easy to match things up
147  */
148 #define TYPE(name, type) type
149 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
150         /* 0x00 */
151         TYPE(PERIPHC_I2S1,      CLOCK_TYPE_AXPT),
152         TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
153         TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
154         TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PC2CC3M),
155         TYPE(PERIPHC_PWM,       CLOCK_TYPE_PC2CC3S_T),
156         TYPE(PERIPHC_05h,       CLOCK_TYPE_NONE),
157         TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PC2CC3M_T),
158         TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PC2CC3M_T),
159
160         /* 0x08 */
161         TYPE(PERIPHC_08h,       CLOCK_TYPE_NONE),
162         TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PC2CC3M_T16),
163         TYPE(PERIPHC_I2C5,      CLOCK_TYPE_PC2CC3M_T16),
164         TYPE(PERIPHC_0bh,       CLOCK_TYPE_NONE),
165         TYPE(PERIPHC_0ch,       CLOCK_TYPE_NONE),
166         TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PC2CC3M_T),
167         TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
168         TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
169
170         /* 0x10 */
171         TYPE(PERIPHC_10h,       CLOCK_TYPE_NONE),
172         TYPE(PERIPHC_11h,       CLOCK_TYPE_NONE),
173         TYPE(PERIPHC_VI,        CLOCK_TYPE_MC2CC3P_A),
174         TYPE(PERIPHC_13h,       CLOCK_TYPE_NONE),
175         TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PC2CC3M_T),
176         TYPE(PERIPHC_SDMMC2,    CLOCK_TYPE_PC2CC3M_T),
177         TYPE(PERIPHC_16h,       CLOCK_TYPE_NONE),
178         TYPE(PERIPHC_17h,       CLOCK_TYPE_NONE),
179
180         /* 0x18 */
181         TYPE(PERIPHC_18h,       CLOCK_TYPE_NONE),
182         TYPE(PERIPHC_SDMMC4,    CLOCK_TYPE_PC2CC3M_T),
183         TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PC2CC3M_T),
184         TYPE(PERIPHC_1Bh,       CLOCK_TYPE_NONE),
185         TYPE(PERIPHC_1Ch,       CLOCK_TYPE_NONE),
186         TYPE(PERIPHC_HSI,       CLOCK_TYPE_PC2CC3M_T),
187         TYPE(PERIPHC_UART1,     CLOCK_TYPE_PC2CC3M_T),
188         TYPE(PERIPHC_UART2,     CLOCK_TYPE_PC2CC3M_T),
189
190         /* 0x20 */
191         TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MC2CC3P_A),
192         TYPE(PERIPHC_21h,       CLOCK_TYPE_NONE),
193         TYPE(PERIPHC_22h,       CLOCK_TYPE_NONE),
194         TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
195         TYPE(PERIPHC_24h,       CLOCK_TYPE_NONE),
196         TYPE(PERIPHC_25h,       CLOCK_TYPE_NONE),
197         TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PC2CC3M_T16),
198         TYPE(PERIPHC_EMC,       CLOCK_TYPE_MCPTM2C2C3),
199
200         /* 0x28 */
201         TYPE(PERIPHC_UART3,     CLOCK_TYPE_PC2CC3M_T),
202         TYPE(PERIPHC_29h,       CLOCK_TYPE_NONE),
203         TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
204         TYPE(PERIPHC_2bh,       CLOCK_TYPE_NONE),
205         TYPE(PERIPHC_2ch,       CLOCK_TYPE_NONE),
206         TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PC2CC3M_T),
207         TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PC2CC3M_T16),
208         TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PC2CC3M_T),
209
210         /* 0x30 */
211         TYPE(PERIPHC_UART4,     CLOCK_TYPE_PC2CC3M_T),
212         TYPE(PERIPHC_UART5,     CLOCK_TYPE_PC2CC3M_T),
213         TYPE(PERIPHC_VDE,       CLOCK_TYPE_PC2CC3M_T),
214         TYPE(PERIPHC_OWR,       CLOCK_TYPE_PC2CC3M_T),
215         TYPE(PERIPHC_NOR,       CLOCK_TYPE_PC2CC3M_T),
216         TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PC2CC3M_T),
217         TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
218         TYPE(PERIPHC_DTV,       CLOCK_TYPE_NONE),
219
220         /* 0x38 */
221         TYPE(PERIPHC_38h,       CLOCK_TYPE_NONE),
222         TYPE(PERIPHC_39h,       CLOCK_TYPE_NONE),
223         TYPE(PERIPHC_3ah,       CLOCK_TYPE_NONE),
224         TYPE(PERIPHC_3bh,       CLOCK_TYPE_NONE),
225         TYPE(PERIPHC_MSENC,     CLOCK_TYPE_MC2CC3P_A),
226         TYPE(PERIPHC_TSEC,      CLOCK_TYPE_PC2CC3M_T),
227         TYPE(PERIPHC_3eh,       CLOCK_TYPE_NONE),
228         TYPE(PERIPHC_OSC,       CLOCK_TYPE_NONE),
229
230         /* 0x40 */
231         TYPE(PERIPHC_40h,       CLOCK_TYPE_NONE),       /* start with 0x3b0 */
232         TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PC2CC3M_T),
233         TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PC2CC3T_S),
234         TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
235         TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
236         TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PC2CC3M_T16),
237         TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PC2CC3M_T),
238         TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PC2CC3M_T),
239
240         /* 0x48 */
241         TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_AC2CC3P_TS2),
242         TYPE(PERIPHC_49h,       CLOCK_TYPE_NONE),
243         TYPE(PERIPHC_DAM0,      CLOCK_TYPE_AC2CC3P_TS2),
244         TYPE(PERIPHC_DAM1,      CLOCK_TYPE_AC2CC3P_TS2),
245         TYPE(PERIPHC_DAM2,      CLOCK_TYPE_AC2CC3P_TS2),
246         TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
247         TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PC2CC3S_T),
248         TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
249
250         /* 0x50 */
251         TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
252         TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
253         TYPE(PERIPHC_52h,       CLOCK_TYPE_NONE),
254         TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PC2CC3S_T),
255         TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
256         TYPE(PERIPHC_55h,       CLOCK_TYPE_NONE),
257         TYPE(PERIPHC_56h,       CLOCK_TYPE_NONE),
258         TYPE(PERIPHC_57h,       CLOCK_TYPE_NONE),
259
260         /* 0x58 */
261         TYPE(PERIPHC_58h,       CLOCK_TYPE_NONE),
262         TYPE(PERIPHC_59h,       CLOCK_TYPE_NONE),
263         TYPE(PERIPHC_5ah,       CLOCK_TYPE_NONE),
264         TYPE(PERIPHC_5bh,       CLOCK_TYPE_NONE),
265         TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),
266         TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
267         TYPE(PERIPHC_HDA,       CLOCK_TYPE_PC2CC3M_T),
268         TYPE(PERIPHC_5fh,       CLOCK_TYPE_NONE),
269
270         /* 0x60 */
271         TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
272         TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
273         TYPE(PERIPHC_XUSB_FS,   CLOCK_TYPE_NONE),
274         TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
275         TYPE(PERIPHC_XUSB_SS,   CLOCK_TYPE_NONE),
276         TYPE(PERIPHC_CILAB,     CLOCK_TYPE_NONE),
277         TYPE(PERIPHC_CILCD,     CLOCK_TYPE_NONE),
278         TYPE(PERIPHC_CILE,      CLOCK_TYPE_NONE),
279
280         /* 0x68 */
281         TYPE(PERIPHC_DSIA_LP,   CLOCK_TYPE_NONE),
282         TYPE(PERIPHC_DSIB_LP,   CLOCK_TYPE_NONE),
283         TYPE(PERIPHC_ENTROPY,   CLOCK_TYPE_NONE),
284         TYPE(PERIPHC_DVFS_REF,  CLOCK_TYPE_NONE),
285         TYPE(PERIPHC_DVFS_SOC,  CLOCK_TYPE_NONE),
286         TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
287         TYPE(PERIPHC_ADX0,      CLOCK_TYPE_NONE),
288         TYPE(PERIPHC_AMX0,      CLOCK_TYPE_NONE),
289
290         /* 0x70 */
291         TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
292         TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
293         TYPE(PERIPHC_72h,       CLOCK_TYPE_NONE),
294         TYPE(PERIPHC_73h,       CLOCK_TYPE_NONE),
295         TYPE(PERIPHC_74h,       CLOCK_TYPE_NONE),
296         TYPE(PERIPHC_75h,       CLOCK_TYPE_NONE),
297         TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
298         TYPE(PERIPHC_I2C6,      CLOCK_TYPE_PC2CC3M_T16),
299
300         /* 0x78 */
301         TYPE(PERIPHC_78h,       CLOCK_TYPE_NONE),
302         TYPE(PERIPHC_EMC_DLL,   CLOCK_TYPE_MCPTM2C2C3),
303         TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
304         TYPE(PERIPHC_CLK72MHZ,  CLOCK_TYPE_NONE),
305         TYPE(PERIPHC_ADX1,      CLOCK_TYPE_AC2CC3P_TS2),
306         TYPE(PERIPHC_AMX1,      CLOCK_TYPE_AC2CC3P_TS2),
307         TYPE(PERIPHC_VIC,       CLOCK_TYPE_NONE),
308         TYPE(PERIPHC_7Fh,       CLOCK_TYPE_NONE),
309 };
310
311 /*
312  * This array translates a periph_id to a periphc_internal_id
313  *
314  * Not present/matched up:
315  *      uint vi_sensor;  _VI_SENSOR_0,          0x1A8
316  *      SPDIF - which is both 0x08 and 0x0c
317  *
318  */
319 #define NONE(name) (-1)
320 #define OFFSET(name, value) PERIPHC_ ## name
321 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
322         /* Low word: 31:0 */
323         NONE(CPU),
324         NONE(COP),
325         NONE(TRIGSYS),
326         NONE(ISPB),
327         NONE(RESERVED4),
328         NONE(TMR),
329         PERIPHC_UART1,
330         PERIPHC_UART2,  /* and vfir 0x68 */
331
332         /* 8 */
333         NONE(GPIO),
334         PERIPHC_SDMMC2,
335         PERIPHC_SPDIF_IN,
336         PERIPHC_I2S1,
337         PERIPHC_I2C1,
338         NONE(RESERVED13),
339         PERIPHC_SDMMC1,
340         PERIPHC_SDMMC4,
341
342         /* 16 */
343         NONE(TCW),
344         PERIPHC_PWM,
345         PERIPHC_I2S2,
346         NONE(RESERVED19),
347         PERIPHC_VI,
348         NONE(RESERVED21),
349         NONE(USBD),
350         NONE(ISP),
351
352         /* 24 */
353         NONE(RESERVED24),
354         NONE(RESERVED25),
355         PERIPHC_DISP2,
356         PERIPHC_DISP1,
357         PERIPHC_HOST1X,
358         NONE(VCP),
359         PERIPHC_I2S0,
360         NONE(CACHE2),
361
362         /* Middle word: 63:32 */
363         NONE(MEM),
364         NONE(AHBDMA),
365         NONE(APBDMA),
366         NONE(RESERVED35),
367         NONE(RESERVED36),
368         NONE(STAT_MON),
369         NONE(RESERVED38),
370         NONE(FUSE),
371
372         /* 40 */
373         NONE(KFUSE),
374         PERIPHC_SBC1,           /* SBCx = SPIx */
375         PERIPHC_NOR,
376         NONE(RESERVED43),
377         PERIPHC_SBC2,
378         NONE(XIO),
379         PERIPHC_SBC3,
380         PERIPHC_I2C5,
381
382         /* 48 */
383         NONE(DSI),
384         NONE(RESERVED49),
385         PERIPHC_HSI,
386         PERIPHC_HDMI,
387         NONE(CSI),
388         NONE(RESERVED53),
389         PERIPHC_I2C2,
390         PERIPHC_UART3,
391
392         /* 56 */
393         NONE(MIPI_CAL),
394         PERIPHC_EMC,
395         NONE(USB2),
396         NONE(USB3),
397         NONE(RESERVED60),
398         PERIPHC_VDE,
399         NONE(BSEA),
400         NONE(BSEV),
401
402         /* Upper word 95:64 */
403         NONE(RESERVED64),
404         PERIPHC_UART4,
405         PERIPHC_UART5,
406         PERIPHC_I2C3,
407         PERIPHC_SBC4,
408         PERIPHC_SDMMC3,
409         NONE(PCIE),
410         PERIPHC_OWR,
411
412         /* 72 */
413         NONE(AFI),
414         PERIPHC_CSITE,
415         NONE(PCIEXCLK),
416         NONE(AVPUCQ),
417         NONE(LA),
418         NONE(TRACECLKIN),
419         NONE(SOC_THERM),
420         NONE(DTV),
421
422         /* 80 */
423         NONE(RESERVED80),
424         PERIPHC_I2CSLOW,
425         NONE(DSIB),
426         PERIPHC_TSEC,
427         NONE(RESERVED84),
428         NONE(RESERVED85),
429         NONE(RESERVED86),
430         NONE(EMUCIF),
431
432         /* 88 */
433         NONE(RESERVED88),
434         NONE(XUSB_HOST),
435         NONE(RESERVED90),
436         PERIPHC_MSENC,
437         NONE(RESERVED92),
438         NONE(RESERVED93),
439         NONE(RESERVED94),
440         NONE(XUSB_DEV),
441
442         /* V word: 31:0 */
443         NONE(CPUG),
444         NONE(CPULP),
445         NONE(V_RESERVED2),
446         PERIPHC_MSELECT,
447         NONE(V_RESERVED4),
448         PERIPHC_I2S3,
449         PERIPHC_I2S4,
450         PERIPHC_I2C4,
451
452         /* 104 */
453         PERIPHC_SBC5,
454         PERIPHC_SBC6,
455         PERIPHC_AUDIO,
456         NONE(APBIF),
457         PERIPHC_DAM0,
458         PERIPHC_DAM1,
459         PERIPHC_DAM2,
460         PERIPHC_HDA2CODEC2X,
461
462         /* 112 */
463         NONE(ATOMICS),
464         NONE(V_RESERVED17),
465         NONE(V_RESERVED18),
466         NONE(V_RESERVED19),
467         NONE(V_RESERVED20),
468         NONE(V_RESERVED21),
469         NONE(V_RESERVED22),
470         PERIPHC_ACTMON,
471
472         /* 120 */
473         NONE(EXTPERIPH1),
474         NONE(EXTPERIPH2),
475         NONE(EXTPERIPH3),
476         NONE(OOB),
477         PERIPHC_SATA,
478         PERIPHC_HDA,
479         NONE(TZRAM),
480         NONE(SE),
481
482         /* W word: 31:0 */
483         NONE(HDA2HDMICODEC),
484         NONE(SATACOLD),
485         NONE(W_RESERVED2),
486         NONE(W_RESERVED3),
487         NONE(W_RESERVED4),
488         NONE(W_RESERVED5),
489         NONE(W_RESERVED6),
490         NONE(W_RESERVED7),
491
492         /* 136 */
493         NONE(CEC),
494         NONE(W_RESERVED9),
495         NONE(W_RESERVED10),
496         NONE(W_RESERVED11),
497         NONE(W_RESERVED12),
498         NONE(W_RESERVED13),
499         NONE(XUSB_PADCTL),
500         NONE(W_RESERVED15),
501
502         /* 144 */
503         NONE(W_RESERVED16),
504         NONE(W_RESERVED17),
505         NONE(W_RESERVED18),
506         NONE(W_RESERVED19),
507         NONE(W_RESERVED20),
508         NONE(ENTROPY),
509         NONE(DDS),
510         NONE(W_RESERVED23),
511
512         /* 152 */
513         NONE(DP2),
514         NONE(AMX0),
515         NONE(ADX0),
516         NONE(DVFS),
517         NONE(XUSB_SS),
518         NONE(W_RESERVED29),
519         NONE(W_RESERVED30),
520         NONE(W_RESERVED31),
521
522         /* X word: 31:0 */
523         NONE(SPARE),
524         NONE(X_RESERVED1),
525         NONE(X_RESERVED2),
526         NONE(X_RESERVED3),
527         NONE(CAM_MCLK),
528         NONE(CAM_MCLK2),
529         PERIPHC_I2C6,
530         NONE(X_RESERVED7),
531
532         /* 168 */
533         NONE(X_RESERVED8),
534         NONE(X_RESERVED9),
535         NONE(X_RESERVED10),
536         NONE(VIM2_CLK),
537         NONE(X_RESERVED12),
538         NONE(X_RESERVED13),
539         NONE(EMC_DLL),
540         NONE(X_RESERVED15),
541
542         /* 176 */
543         NONE(HDMI_AUDIO),
544         NONE(CLK72MHZ),
545         NONE(VIC),
546         NONE(X_RESERVED19),
547         NONE(ADX1),
548         NONE(DPAUX),
549         NONE(SOR0),
550         NONE(X_RESERVED23),
551
552         /* 184 */
553         NONE(GPU),
554         NONE(AMX1),
555         NONE(X_RESERVED26),
556         NONE(X_RESERVED27),
557         NONE(X_RESERVED28),
558         NONE(X_RESERVED29),
559         NONE(X_RESERVED30),
560         NONE(X_RESERVED31),
561 };
562
563 /*
564  * Get the oscillator frequency, from the corresponding hardware configuration
565  * field. Note that Tegra30+ support 3 new higher freqs, but we map back
566  * to the old T20 freqs. Support for the higher oscillators is TBD.
567  */
568 enum clock_osc_freq clock_get_osc_freq(void)
569 {
570         struct clk_rst_ctlr *clkrst =
571                         (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
572         u32 reg;
573
574         reg = readl(&clkrst->crc_osc_ctrl);
575         reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
576
577         if (reg & 1)                            /* one of the newer freqs */
578                 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
579
580         return reg >> 2;        /* Map to most common (T20) freqs */
581 }
582
583 /* Returns a pointer to the clock source register for a peripheral */
584 u32 *get_periph_source_reg(enum periph_id periph_id)
585 {
586         struct clk_rst_ctlr *clkrst =
587                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
588         enum periphc_internal_id internal_id;
589
590         /* Coresight is a special case */
591         if (periph_id == PERIPH_ID_CSI)
592                 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
593
594         assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
595         internal_id = periph_id_to_internal_id[periph_id];
596         assert(internal_id != -1);
597         if (internal_id >= PERIPHC_VW_FIRST) {
598                 internal_id -= PERIPHC_VW_FIRST;
599                 return &clkrst->crc_clk_src_vw[internal_id];
600         } else {
601                 return &clkrst->crc_clk_src[internal_id];
602         }
603 }
604
605 /**
606  * Given a peripheral ID and the required source clock, this returns which
607  * value should be programmed into the source mux for that peripheral.
608  *
609  * There is special code here to handle the one source type with 5 sources.
610  *
611  * @param periph_id     peripheral to start
612  * @param source        PLL id of required parent clock
613  * @param mux_bits      Set to number of bits in mux register: 2 or 4
614  * @param divider_bits Set to number of divider bits (8 or 16)
615  * @return mux value (0-4, or -1 if not found)
616  */
617 int get_periph_clock_source(enum periph_id periph_id,
618         enum clock_id parent, int *mux_bits, int *divider_bits)
619 {
620         enum clock_type_id type;
621         enum periphc_internal_id internal_id;
622         int mux;
623
624         assert(clock_periph_id_isvalid(periph_id));
625
626         internal_id = periph_id_to_internal_id[periph_id];
627         assert(periphc_internal_id_isvalid(internal_id));
628
629         type = clock_periph_type[internal_id];
630         assert(clock_type_id_isvalid(type));
631
632         *mux_bits = clock_source[type][CLOCK_MAX_MUX];
633
634         if (type == CLOCK_TYPE_PC2CC3M_T16)
635                 *divider_bits = 16;
636         else
637                 *divider_bits = 8;
638
639         for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
640                 if (clock_source[type][mux] == parent)
641                         return mux;
642
643         /* if we get here, either us or the caller has made a mistake */
644         printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
645                parent);
646         return -1;
647 }
648
649 void clock_set_enable(enum periph_id periph_id, int enable)
650 {
651         struct clk_rst_ctlr *clkrst =
652                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
653         u32 *clk;
654         u32 reg;
655
656         /* Enable/disable the clock to this peripheral */
657         assert(clock_periph_id_isvalid(periph_id));
658         if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
659                 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
660         else
661                 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
662         reg = readl(clk);
663         if (enable)
664                 reg |= PERIPH_MASK(periph_id);
665         else
666                 reg &= ~PERIPH_MASK(periph_id);
667         writel(reg, clk);
668 }
669
670 void reset_set_enable(enum periph_id periph_id, int enable)
671 {
672         struct clk_rst_ctlr *clkrst =
673                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
674         u32 *reset;
675         u32 reg;
676
677         /* Enable/disable reset to the peripheral */
678         assert(clock_periph_id_isvalid(periph_id));
679         if (periph_id < PERIPH_ID_VW_FIRST)
680                 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
681         else
682                 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
683         reg = readl(reset);
684         if (enable)
685                 reg |= PERIPH_MASK(periph_id);
686         else
687                 reg &= ~PERIPH_MASK(periph_id);
688         writel(reg, reset);
689 }
690
691 #ifdef CONFIG_OF_CONTROL
692 /*
693  * Convert a device tree clock ID to our peripheral ID. They are mostly
694  * the same but we are very cautious so we check that a valid clock ID is
695  * provided.
696  *
697  * @param clk_id    Clock ID according to tegra124 device tree binding
698  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
699  */
700 enum periph_id clk_id_to_periph_id(int clk_id)
701 {
702         if (clk_id > PERIPH_ID_COUNT)
703                 return PERIPH_ID_NONE;
704
705         switch (clk_id) {
706         case PERIPH_ID_RESERVED4:
707         case PERIPH_ID_RESERVED25:
708         case PERIPH_ID_RESERVED35:
709         case PERIPH_ID_RESERVED36:
710         case PERIPH_ID_RESERVED38:
711         case PERIPH_ID_RESERVED43:
712         case PERIPH_ID_RESERVED49:
713         case PERIPH_ID_RESERVED53:
714         case PERIPH_ID_RESERVED64:
715         case PERIPH_ID_RESERVED84:
716         case PERIPH_ID_RESERVED85:
717         case PERIPH_ID_RESERVED86:
718         case PERIPH_ID_RESERVED88:
719         case PERIPH_ID_RESERVED90:
720         case PERIPH_ID_RESERVED92:
721         case PERIPH_ID_RESERVED93:
722         case PERIPH_ID_RESERVED94:
723         case PERIPH_ID_V_RESERVED2:
724         case PERIPH_ID_V_RESERVED4:
725         case PERIPH_ID_V_RESERVED17:
726         case PERIPH_ID_V_RESERVED18:
727         case PERIPH_ID_V_RESERVED19:
728         case PERIPH_ID_V_RESERVED20:
729         case PERIPH_ID_V_RESERVED21:
730         case PERIPH_ID_V_RESERVED22:
731         case PERIPH_ID_W_RESERVED2:
732         case PERIPH_ID_W_RESERVED3:
733         case PERIPH_ID_W_RESERVED4:
734         case PERIPH_ID_W_RESERVED5:
735         case PERIPH_ID_W_RESERVED6:
736         case PERIPH_ID_W_RESERVED7:
737         case PERIPH_ID_W_RESERVED9:
738         case PERIPH_ID_W_RESERVED10:
739         case PERIPH_ID_W_RESERVED11:
740         case PERIPH_ID_W_RESERVED12:
741         case PERIPH_ID_W_RESERVED13:
742         case PERIPH_ID_W_RESERVED15:
743         case PERIPH_ID_W_RESERVED16:
744         case PERIPH_ID_W_RESERVED17:
745         case PERIPH_ID_W_RESERVED18:
746         case PERIPH_ID_W_RESERVED19:
747         case PERIPH_ID_W_RESERVED20:
748         case PERIPH_ID_W_RESERVED23:
749         case PERIPH_ID_W_RESERVED29:
750         case PERIPH_ID_W_RESERVED30:
751         case PERIPH_ID_W_RESERVED31:
752                 return PERIPH_ID_NONE;
753         default:
754                 return clk_id;
755         }
756 }
757 #endif /* CONFIG_OF_CONTROL */
758
759 void clock_early_init(void)
760 {
761         struct clk_rst_ctlr *clkrst =
762                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
763
764         tegra30_set_up_pllp();
765
766         /*
767          * PLLC output frequency set to 600Mhz
768          * PLLD output frequency set to 925Mhz
769          */
770         switch (clock_get_osc_freq()) {
771         case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
772                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
773                 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
774                 break;
775
776         case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
777                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
778                 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
779                 break;
780
781         case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
782                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
783                 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
784                 break;
785         case CLOCK_OSC_FREQ_19_2:
786         default:
787                 /*
788                  * These are not supported. It is too early to print a
789                  * message and the UART likely won't work anyway due to the
790                  * oscillator being wrong.
791                  */
792                 break;
793         }
794
795         /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
796         writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
797
798         /* PLLC_MISC: Set LOCK_ENABLE */
799         writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
800         udelay(2);
801
802         /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
803         writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
804         udelay(2);
805 }
806
807 void arch_timer_init(void)
808 {
809         struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
810         u32 freq, val;
811
812         freq = clock_get_rate(CLOCK_ID_OSC);
813         debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
814
815         /* ARM CNTFRQ */
816         asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
817
818         /* Only Tegra114+ has the System Counter regs */
819         debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
820         writel(freq, &sysctr->cntfid0);
821
822         val = readl(&sysctr->cntcr);
823         val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
824         writel(val, &sysctr->cntcr);
825         debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
826 }