3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 pin multiplexing functions */
12 #include <asm/arch/tegra.h>
13 #include <asm/arch/pinmux.h>
15 struct tegra_pingroup_desc {
17 enum pmux_func funcs[4];
18 enum pmux_vddio vddio;
22 #define PMUX_MUXCTL_SHIFT 0
23 #define PMUX_PULL_SHIFT 2
24 #define PMUX_TRISTATE_SHIFT 4
25 #define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
26 #define PMUX_IO_SHIFT 5
27 #define PMUX_OD_SHIFT 6
28 #define PMUX_LOCK_SHIFT 7
29 #define PMUX_IO_RESET_SHIFT 8
30 #define PMUX_RCV_SEL_SHIFT 9
32 #define PGRP_HSM_SHIFT 2
33 #define PGRP_SCHMT_SHIFT 3
34 #define PGRP_LPMD_SHIFT 4
35 #define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
36 #define PGRP_DRVDN_SHIFT 12
37 #define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
38 #define PGRP_DRVUP_SHIFT 20
39 #define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
40 #define PGRP_SLWR_SHIFT 28
41 #define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
42 #define PGRP_SLWF_SHIFT 30
43 #define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
45 /* Convenient macro for defining pin group properties */
46 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
48 .vddio = PMUX_VDDIO_ ## vdd, \
55 .io = PMUX_PIN_ ## iod, \
58 /* Input and output pins */
59 #define PINI(pg_name, vdd, f0, f1, f2, f3) \
60 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
61 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
62 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
64 /* A pin group number which is not used */
65 #define PIN_RESERVED \
66 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
68 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
69 /* NAME VDD f0 f1 f2 f3 */
70 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
71 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
72 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
73 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
74 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
75 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
76 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
77 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
78 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
79 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
80 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
81 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
82 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
83 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
84 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
85 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
86 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
87 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
88 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
89 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
90 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
91 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
92 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
93 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
94 PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
96 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
97 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
98 PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
138 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
139 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
140 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
141 PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
159 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
160 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
161 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
162 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
163 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
164 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
165 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
166 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
167 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
168 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
169 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
170 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
171 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
172 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
173 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
174 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
175 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
176 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
177 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
178 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
179 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
180 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
181 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
182 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
183 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
184 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
185 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
186 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
187 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
188 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
189 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
190 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
191 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
192 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
193 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
194 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
195 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
196 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
197 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
198 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
199 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
200 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
201 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
202 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
203 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
204 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
205 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
206 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
207 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
208 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
209 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
210 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
211 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
212 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
213 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
214 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
215 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
216 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
217 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
218 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
219 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
220 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
221 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
222 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
223 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
224 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
225 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
226 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
227 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
228 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
229 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
230 PIN_RESERVED, /* Reserved: 0x3280 */
231 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
232 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
233 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
234 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
235 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
236 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
237 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
238 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
239 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
240 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
241 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
242 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
243 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
244 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
245 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
246 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
247 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
248 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
249 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
250 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
251 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
252 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
253 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
254 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
255 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
256 PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
261 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
262 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
263 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
264 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
265 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
266 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
267 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
268 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
269 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
270 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
271 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
272 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
273 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
274 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
275 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
276 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
277 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
278 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
279 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
280 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
281 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
282 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
283 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
284 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
285 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
286 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
287 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
288 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
289 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
290 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
291 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
292 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
293 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
294 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
295 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
296 PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
298 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
299 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
300 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
301 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
302 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
303 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
304 PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
318 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
319 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
320 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
321 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
322 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
323 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
324 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
325 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
326 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
327 PIN_RESERVED, /* Reserved: 0x3404 */
328 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
331 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
333 struct pmux_tri_ctlr *pmt =
334 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
335 u32 *tri = &pmt->pmt_ctl[pin];
338 /* Error check on pin */
339 assert(pmux_pingrp_isvalid(pin));
343 reg |= PMUX_TRISTATE_MASK;
345 reg &= ~PMUX_TRISTATE_MASK;
349 void pinmux_tristate_enable(enum pmux_pingrp pin)
351 pinmux_set_tristate(pin, 1);
354 void pinmux_tristate_disable(enum pmux_pingrp pin)
356 pinmux_set_tristate(pin, 0);
359 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
361 struct pmux_tri_ctlr *pmt =
362 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
363 u32 *pull = &pmt->pmt_ctl[pin];
366 /* Error check on pin and pupd */
367 assert(pmux_pingrp_isvalid(pin));
368 assert(pmux_pin_pupd_isvalid(pupd));
371 reg &= ~(0x3 << PMUX_PULL_SHIFT);
372 reg |= (pupd << PMUX_PULL_SHIFT);
376 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
378 struct pmux_tri_ctlr *pmt =
379 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
380 u32 *muxctl = &pmt->pmt_ctl[pin];
384 /* Error check on pin and func */
385 assert(pmux_pingrp_isvalid(pin));
386 assert(pmux_func_isvalid(func));
388 if (func & PMUX_FUNC_RSVD1) {
391 /* Search for the appropriate function */
392 for (i = 0; i < 4; i++) {
393 if (tegra_soc_pingroups[pin].funcs[i] == func) {
402 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
403 reg |= (mux << PMUX_MUXCTL_SHIFT);
407 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
409 struct pmux_tri_ctlr *pmt =
410 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
411 u32 *pin_io = &pmt->pmt_ctl[pin];
414 /* Error check on pin and io */
415 assert(pmux_pingrp_isvalid(pin));
416 assert(pmux_pin_io_isvalid(io));
419 reg &= ~(0x1 << PMUX_IO_SHIFT);
420 reg |= (io & 0x1) << PMUX_IO_SHIFT;
424 static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
426 struct pmux_tri_ctlr *pmt =
427 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
428 u32 *pin_lock = &pmt->pmt_ctl[pin];
431 /* Error check on pin and lock */
432 assert(pmux_pingrp_isvalid(pin));
433 assert(pmux_pin_lock_isvalid(lock));
435 if (lock == PMUX_PIN_LOCK_DEFAULT)
438 reg = readl(pin_lock);
439 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
440 if (lock == PMUX_PIN_LOCK_ENABLE) {
441 reg |= (0x1 << PMUX_LOCK_SHIFT);
443 /* lock == DISABLE, which isn't possible */
444 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
447 writel(reg, pin_lock);
452 static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
454 struct pmux_tri_ctlr *pmt =
455 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
456 u32 *pin_od = &pmt->pmt_ctl[pin];
459 /* Error check on pin and od */
460 assert(pmux_pingrp_isvalid(pin));
461 assert(pmux_pin_od_isvalid(od));
463 if (od == PMUX_PIN_OD_DEFAULT)
467 reg &= ~(0x1 << PMUX_OD_SHIFT);
468 if (od == PMUX_PIN_OD_ENABLE)
469 reg |= (0x1 << PMUX_OD_SHIFT);
475 static int pinmux_set_ioreset(enum pmux_pingrp pin,
476 enum pmux_pin_ioreset ioreset)
478 struct pmux_tri_ctlr *pmt =
479 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
480 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
483 /* Error check on pin and ioreset */
484 assert(pmux_pingrp_isvalid(pin));
485 assert(pmux_pin_ioreset_isvalid(ioreset));
487 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
490 reg = readl(pin_ioreset);
491 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
492 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
493 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
494 writel(reg, pin_ioreset);
499 static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
500 enum pmux_pin_rcv_sel rcv_sel)
502 struct pmux_tri_ctlr *pmt =
503 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
504 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
507 /* Error check on pin and rcv_sel */
508 assert(pmux_pingrp_isvalid(pin));
509 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
511 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
514 reg = readl(pin_rcv_sel);
515 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
516 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
517 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
518 writel(reg, pin_rcv_sel);
523 void pinmux_config_pingroup(struct pingroup_config *config)
525 enum pmux_pingrp pin = config->pingroup;
527 pinmux_set_func(pin, config->func);
528 pinmux_set_pullupdown(pin, config->pull);
529 pinmux_set_tristate(pin, config->tristate);
530 pinmux_set_io(pin, config->io);
531 pinmux_set_lock(pin, config->lock);
532 pinmux_set_od(pin, config->od);
533 pinmux_set_ioreset(pin, config->ioreset);
534 pinmux_set_rcv_sel(pin, config->rcv_sel);
537 void pinmux_config_table(struct pingroup_config *config, int len)
541 for (i = 0; i < len; i++)
542 pinmux_config_pingroup(&config[i]);
545 static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
547 struct pmux_tri_ctlr *pmt =
548 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
549 u32 *pad_slwf = &pmt->pmt_drive[pad];
552 /* Error check on pad and slwf */
553 assert(pmux_padgrp_isvalid(pad));
554 assert(pmux_pad_slw_isvalid(slwf));
556 /* NONE means unspecified/do not change/use POR value */
557 if (slwf == PGRP_SLWF_NONE)
560 reg = readl(pad_slwf);
561 reg &= ~PGRP_SLWF_MASK;
562 reg |= (slwf << PGRP_SLWF_SHIFT);
563 writel(reg, pad_slwf);
568 static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
570 struct pmux_tri_ctlr *pmt =
571 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
572 u32 *pad_slwr = &pmt->pmt_drive[pad];
575 /* Error check on pad and slwr */
576 assert(pmux_padgrp_isvalid(pad));
577 assert(pmux_pad_slw_isvalid(slwr));
579 /* NONE means unspecified/do not change/use POR value */
580 if (slwr == PGRP_SLWR_NONE)
583 reg = readl(pad_slwr);
584 reg &= ~PGRP_SLWR_MASK;
585 reg |= (slwr << PGRP_SLWR_SHIFT);
586 writel(reg, pad_slwr);
591 static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
593 struct pmux_tri_ctlr *pmt =
594 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
595 u32 *pad_drvup = &pmt->pmt_drive[pad];
598 /* Error check on pad and drvup */
599 assert(pmux_padgrp_isvalid(pad));
600 assert(pmux_pad_drv_isvalid(drvup));
602 /* NONE means unspecified/do not change/use POR value */
603 if (drvup == PGRP_DRVUP_NONE)
606 reg = readl(pad_drvup);
607 reg &= ~PGRP_DRVUP_MASK;
608 reg |= (drvup << PGRP_DRVUP_SHIFT);
609 writel(reg, pad_drvup);
614 static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
616 struct pmux_tri_ctlr *pmt =
617 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
618 u32 *pad_drvdn = &pmt->pmt_drive[pad];
621 /* Error check on pad and drvdn */
622 assert(pmux_padgrp_isvalid(pad));
623 assert(pmux_pad_drv_isvalid(drvdn));
625 /* NONE means unspecified/do not change/use POR value */
626 if (drvdn == PGRP_DRVDN_NONE)
629 reg = readl(pad_drvdn);
630 reg &= ~PGRP_DRVDN_MASK;
631 reg |= (drvdn << PGRP_DRVDN_SHIFT);
632 writel(reg, pad_drvdn);
637 static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
639 struct pmux_tri_ctlr *pmt =
640 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
641 u32 *pad_lpmd = &pmt->pmt_drive[pad];
644 /* Error check pad and lpmd value */
645 assert(pmux_padgrp_isvalid(pad));
646 assert(pmux_pad_lpmd_isvalid(lpmd));
648 /* NONE means unspecified/do not change/use POR value */
649 if (lpmd == PGRP_LPMD_NONE)
652 reg = readl(pad_lpmd);
653 reg &= ~PGRP_LPMD_MASK;
654 reg |= (lpmd << PGRP_LPMD_SHIFT);
655 writel(reg, pad_lpmd);
660 static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
662 struct pmux_tri_ctlr *pmt =
663 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
664 u32 *pad_schmt = &pmt->pmt_drive[pad];
667 /* Error check pad */
668 assert(pmux_padgrp_isvalid(pad));
670 /* NONE means unspecified/do not change/use POR value */
671 if (schmt == PGRP_SCHMT_NONE)
674 reg = readl(pad_schmt);
675 reg &= ~(1 << PGRP_SCHMT_SHIFT);
676 if (schmt == PGRP_SCHMT_ENABLE)
677 reg |= (0x1 << PGRP_SCHMT_SHIFT);
678 writel(reg, pad_schmt);
682 static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
684 struct pmux_tri_ctlr *pmt =
685 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
686 u32 *pad_hsm = &pmt->pmt_drive[pad];
689 /* Error check pad */
690 assert(pmux_padgrp_isvalid(pad));
692 /* NONE means unspecified/do not change/use POR value */
693 if (hsm == PGRP_HSM_NONE)
696 reg = readl(pad_hsm);
697 reg &= ~(1 << PGRP_HSM_SHIFT);
698 if (hsm == PGRP_HSM_ENABLE)
699 reg |= (0x1 << PGRP_HSM_SHIFT);
700 writel(reg, pad_hsm);
705 void padctrl_config_pingroup(struct padctrl_config *config)
707 enum pdrive_pingrp pad = config->padgrp;
709 padgrp_set_drvup_slwf(pad, config->slwf);
710 padgrp_set_drvdn_slwr(pad, config->slwr);
711 padgrp_set_drvup(pad, config->drvup);
712 padgrp_set_drvdn(pad, config->drvdn);
713 padgrp_set_lpmd(pad, config->lpmd);
714 padgrp_set_schmt(pad, config->schmt);
715 padgrp_set_hsm(pad, config->hsm);
718 void padgrp_config_table(struct padctrl_config *config, int len)
722 for (i = 0; i < len; i++)
723 padctrl_config_pingroup(&config[i]);