3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 pin multiplexing functions */
12 #include <asm/arch/tegra.h>
13 #include <asm/arch/pinmux.h>
15 struct tegra_pingroup_desc {
17 enum pmux_func funcs[4];
21 #define PMUX_MUXCTL_SHIFT 0
22 #define PMUX_PULL_SHIFT 2
23 #define PMUX_TRISTATE_SHIFT 4
24 #define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
25 #define PMUX_IO_SHIFT 5
26 #define PMUX_OD_SHIFT 6
27 #define PMUX_LOCK_SHIFT 7
28 #define PMUX_IO_RESET_SHIFT 8
29 #define PMUX_RCV_SEL_SHIFT 9
31 #define PGRP_HSM_SHIFT 2
32 #define PGRP_SCHMT_SHIFT 3
33 #define PGRP_LPMD_SHIFT 4
34 #define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
35 #define PGRP_DRVDN_SHIFT 12
36 #define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
37 #define PGRP_DRVUP_SHIFT 20
38 #define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
39 #define PGRP_SLWR_SHIFT 28
40 #define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
41 #define PGRP_SLWF_SHIFT 30
42 #define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
44 /* Convenient macro for defining pin group properties */
45 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
53 .io = PMUX_PIN_ ## iod, \
56 /* Input and output pins */
57 #define PINI(pg_name, vdd, f0, f1, f2, f3) \
58 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
59 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
60 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
62 /* A pin group number which is not used */
63 #define PIN_RESERVED \
64 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
66 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
67 /* NAME VDD f0 f1 f2 f3 */
68 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
69 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
70 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
71 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
72 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
73 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
74 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
75 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
76 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
77 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
78 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
79 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
80 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
81 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
82 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
83 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
84 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
85 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
86 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
87 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
88 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
89 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
90 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
91 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
92 PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
94 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
95 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
96 PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
136 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
137 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
138 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
139 PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
157 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
158 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
159 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
160 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
161 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
162 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
163 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
164 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
165 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
166 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
167 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
168 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
169 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
170 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
171 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
172 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
173 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
174 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
175 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
176 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
177 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
178 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
179 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
180 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
181 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
182 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
183 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
184 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
185 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
186 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
187 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
188 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
189 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
190 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
191 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
192 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
193 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
194 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
195 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
196 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
197 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
198 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
199 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
200 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
201 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
202 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
203 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
204 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
205 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
206 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
207 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
208 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
209 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
210 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
211 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
212 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
213 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
214 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
215 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
216 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
217 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
218 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
219 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
220 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
221 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
222 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
223 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
224 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
225 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
226 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
227 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
228 PIN_RESERVED, /* Reserved: 0x3280 */
229 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
230 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
231 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
232 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
233 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
234 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
235 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
236 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
237 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
238 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
239 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
240 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
241 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
242 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
243 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
244 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
245 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
246 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
247 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
248 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
249 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
250 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
251 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
252 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
253 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
254 PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
259 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
260 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
261 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
262 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
263 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
264 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
265 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
266 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
267 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
268 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
269 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
270 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
271 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
272 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
273 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
274 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
275 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
276 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
277 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
278 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
279 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
280 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
281 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
282 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
283 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
284 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
285 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
286 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
287 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
288 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
289 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
290 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
291 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
292 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
293 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
294 PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
296 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
297 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
298 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
299 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
300 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
301 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
302 PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
316 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
317 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
318 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
319 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
320 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
321 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
322 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
323 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
324 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
325 PIN_RESERVED, /* Reserved: 0x3404 */
326 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
329 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
331 struct pmux_tri_ctlr *pmt =
332 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
333 u32 *tri = &pmt->pmt_ctl[pin];
336 /* Error check on pin */
337 assert(pmux_pingrp_isvalid(pin));
341 reg |= PMUX_TRISTATE_MASK;
343 reg &= ~PMUX_TRISTATE_MASK;
347 void pinmux_tristate_enable(enum pmux_pingrp pin)
349 pinmux_set_tristate(pin, 1);
352 void pinmux_tristate_disable(enum pmux_pingrp pin)
354 pinmux_set_tristate(pin, 0);
357 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
359 struct pmux_tri_ctlr *pmt =
360 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
361 u32 *pull = &pmt->pmt_ctl[pin];
364 /* Error check on pin and pupd */
365 assert(pmux_pingrp_isvalid(pin));
366 assert(pmux_pin_pupd_isvalid(pupd));
369 reg &= ~(0x3 << PMUX_PULL_SHIFT);
370 reg |= (pupd << PMUX_PULL_SHIFT);
374 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
376 struct pmux_tri_ctlr *pmt =
377 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
378 u32 *muxctl = &pmt->pmt_ctl[pin];
382 /* Error check on pin and func */
383 assert(pmux_pingrp_isvalid(pin));
384 assert(pmux_func_isvalid(func));
386 if (func & PMUX_FUNC_RSVD1) {
389 /* Search for the appropriate function */
390 for (i = 0; i < 4; i++) {
391 if (tegra_soc_pingroups[pin].funcs[i] == func) {
400 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
401 reg |= (mux << PMUX_MUXCTL_SHIFT);
405 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
407 struct pmux_tri_ctlr *pmt =
408 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
409 u32 *pin_io = &pmt->pmt_ctl[pin];
412 /* Error check on pin and io */
413 assert(pmux_pingrp_isvalid(pin));
414 assert(pmux_pin_io_isvalid(io));
417 reg &= ~(0x1 << PMUX_IO_SHIFT);
418 reg |= (io & 0x1) << PMUX_IO_SHIFT;
422 static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
424 struct pmux_tri_ctlr *pmt =
425 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
426 u32 *pin_lock = &pmt->pmt_ctl[pin];
429 /* Error check on pin and lock */
430 assert(pmux_pingrp_isvalid(pin));
431 assert(pmux_pin_lock_isvalid(lock));
433 if (lock == PMUX_PIN_LOCK_DEFAULT)
436 reg = readl(pin_lock);
437 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
438 if (lock == PMUX_PIN_LOCK_ENABLE) {
439 reg |= (0x1 << PMUX_LOCK_SHIFT);
441 /* lock == DISABLE, which isn't possible */
442 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
445 writel(reg, pin_lock);
450 static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
452 struct pmux_tri_ctlr *pmt =
453 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
454 u32 *pin_od = &pmt->pmt_ctl[pin];
457 /* Error check on pin and od */
458 assert(pmux_pingrp_isvalid(pin));
459 assert(pmux_pin_od_isvalid(od));
461 if (od == PMUX_PIN_OD_DEFAULT)
465 reg &= ~(0x1 << PMUX_OD_SHIFT);
466 if (od == PMUX_PIN_OD_ENABLE)
467 reg |= (0x1 << PMUX_OD_SHIFT);
473 static int pinmux_set_ioreset(enum pmux_pingrp pin,
474 enum pmux_pin_ioreset ioreset)
476 struct pmux_tri_ctlr *pmt =
477 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
478 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
481 /* Error check on pin and ioreset */
482 assert(pmux_pingrp_isvalid(pin));
483 assert(pmux_pin_ioreset_isvalid(ioreset));
485 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
488 reg = readl(pin_ioreset);
489 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
490 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
491 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
492 writel(reg, pin_ioreset);
497 static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
498 enum pmux_pin_rcv_sel rcv_sel)
500 struct pmux_tri_ctlr *pmt =
501 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
502 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
505 /* Error check on pin and rcv_sel */
506 assert(pmux_pingrp_isvalid(pin));
507 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
509 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
512 reg = readl(pin_rcv_sel);
513 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
514 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
515 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
516 writel(reg, pin_rcv_sel);
521 void pinmux_config_pingroup(struct pingroup_config *config)
523 enum pmux_pingrp pin = config->pingroup;
525 pinmux_set_func(pin, config->func);
526 pinmux_set_pullupdown(pin, config->pull);
527 pinmux_set_tristate(pin, config->tristate);
528 pinmux_set_io(pin, config->io);
529 pinmux_set_lock(pin, config->lock);
530 pinmux_set_od(pin, config->od);
531 pinmux_set_ioreset(pin, config->ioreset);
532 pinmux_set_rcv_sel(pin, config->rcv_sel);
535 void pinmux_config_table(struct pingroup_config *config, int len)
539 for (i = 0; i < len; i++)
540 pinmux_config_pingroup(&config[i]);
543 static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
545 struct pmux_tri_ctlr *pmt =
546 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
547 u32 *pad_slwf = &pmt->pmt_drive[pad];
550 /* Error check on pad and slwf */
551 assert(pmux_padgrp_isvalid(pad));
552 assert(pmux_pad_slw_isvalid(slwf));
554 /* NONE means unspecified/do not change/use POR value */
555 if (slwf == PGRP_SLWF_NONE)
558 reg = readl(pad_slwf);
559 reg &= ~PGRP_SLWF_MASK;
560 reg |= (slwf << PGRP_SLWF_SHIFT);
561 writel(reg, pad_slwf);
566 static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
568 struct pmux_tri_ctlr *pmt =
569 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
570 u32 *pad_slwr = &pmt->pmt_drive[pad];
573 /* Error check on pad and slwr */
574 assert(pmux_padgrp_isvalid(pad));
575 assert(pmux_pad_slw_isvalid(slwr));
577 /* NONE means unspecified/do not change/use POR value */
578 if (slwr == PGRP_SLWR_NONE)
581 reg = readl(pad_slwr);
582 reg &= ~PGRP_SLWR_MASK;
583 reg |= (slwr << PGRP_SLWR_SHIFT);
584 writel(reg, pad_slwr);
589 static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
591 struct pmux_tri_ctlr *pmt =
592 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
593 u32 *pad_drvup = &pmt->pmt_drive[pad];
596 /* Error check on pad and drvup */
597 assert(pmux_padgrp_isvalid(pad));
598 assert(pmux_pad_drv_isvalid(drvup));
600 /* NONE means unspecified/do not change/use POR value */
601 if (drvup == PGRP_DRVUP_NONE)
604 reg = readl(pad_drvup);
605 reg &= ~PGRP_DRVUP_MASK;
606 reg |= (drvup << PGRP_DRVUP_SHIFT);
607 writel(reg, pad_drvup);
612 static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
614 struct pmux_tri_ctlr *pmt =
615 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
616 u32 *pad_drvdn = &pmt->pmt_drive[pad];
619 /* Error check on pad and drvdn */
620 assert(pmux_padgrp_isvalid(pad));
621 assert(pmux_pad_drv_isvalid(drvdn));
623 /* NONE means unspecified/do not change/use POR value */
624 if (drvdn == PGRP_DRVDN_NONE)
627 reg = readl(pad_drvdn);
628 reg &= ~PGRP_DRVDN_MASK;
629 reg |= (drvdn << PGRP_DRVDN_SHIFT);
630 writel(reg, pad_drvdn);
635 static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
637 struct pmux_tri_ctlr *pmt =
638 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
639 u32 *pad_lpmd = &pmt->pmt_drive[pad];
642 /* Error check pad and lpmd value */
643 assert(pmux_padgrp_isvalid(pad));
644 assert(pmux_pad_lpmd_isvalid(lpmd));
646 /* NONE means unspecified/do not change/use POR value */
647 if (lpmd == PGRP_LPMD_NONE)
650 reg = readl(pad_lpmd);
651 reg &= ~PGRP_LPMD_MASK;
652 reg |= (lpmd << PGRP_LPMD_SHIFT);
653 writel(reg, pad_lpmd);
658 static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
660 struct pmux_tri_ctlr *pmt =
661 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
662 u32 *pad_schmt = &pmt->pmt_drive[pad];
665 /* Error check pad */
666 assert(pmux_padgrp_isvalid(pad));
668 /* NONE means unspecified/do not change/use POR value */
669 if (schmt == PGRP_SCHMT_NONE)
672 reg = readl(pad_schmt);
673 reg &= ~(1 << PGRP_SCHMT_SHIFT);
674 if (schmt == PGRP_SCHMT_ENABLE)
675 reg |= (0x1 << PGRP_SCHMT_SHIFT);
676 writel(reg, pad_schmt);
680 static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
682 struct pmux_tri_ctlr *pmt =
683 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
684 u32 *pad_hsm = &pmt->pmt_drive[pad];
687 /* Error check pad */
688 assert(pmux_padgrp_isvalid(pad));
690 /* NONE means unspecified/do not change/use POR value */
691 if (hsm == PGRP_HSM_NONE)
694 reg = readl(pad_hsm);
695 reg &= ~(1 << PGRP_HSM_SHIFT);
696 if (hsm == PGRP_HSM_ENABLE)
697 reg |= (0x1 << PGRP_HSM_SHIFT);
698 writel(reg, pad_hsm);
703 void padctrl_config_pingroup(struct padctrl_config *config)
705 enum pdrive_pingrp pad = config->padgrp;
707 padgrp_set_drvup_slwf(pad, config->slwf);
708 padgrp_set_drvdn_slwr(pad, config->slwr);
709 padgrp_set_drvup(pad, config->drvup);
710 padgrp_set_drvdn(pad, config->drvdn);
711 padgrp_set_lpmd(pad, config->lpmd);
712 padgrp_set_schmt(pad, config->schmt);
713 padgrp_set_hsm(pad, config->hsm);
716 void padgrp_config_table(struct padctrl_config *config, int len)
720 for (i = 0; i < len; i++)
721 padctrl_config_pingroup(&config[i]);