2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra20 pin multiplexing functions */
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/pinmux.h>
16 * This defines the order of the pin mux control bits in the registers. For
17 * some reason there is no correspendence between the tristate, pin mux and
18 * pullup/pulldown registers.
21 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
40 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
59 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
78 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
97 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
116 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
135 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
158 * And this defines the order of the pullup/pulldown controls which are again
159 * in a different order
162 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
181 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
199 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
218 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
237 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
259 struct tegra_pingroup_desc {
261 enum pmux_func funcs[4];
262 enum pmux_ctlid ctl_id;
263 enum pmux_pullid pull_id;
267 /* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
268 #define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
270 /* Mask value for a tristate (within TRISTATE_REG(id)) */
271 #define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
273 /* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
274 #define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
276 /* Converts a PUCTL id to a shift position */
277 #define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
279 /* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
280 #define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
282 /* Converts a MUXCTL id to a shift position */
283 #define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
285 /* Convenient macro for defining pin group properties */
286 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
298 /* A normal pin group where the mux name and pull-up name match */
299 #define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
300 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
301 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
303 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
304 #define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
305 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
306 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
308 /* A pin group number which is not used */
309 #define PIN_RESERVED \
310 PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
312 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
313 PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
314 PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
315 PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
316 PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
317 PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
318 PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
319 PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
321 PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
323 PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
324 PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
325 PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
326 PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
327 PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
328 PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
329 PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
330 PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
332 PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
334 PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
335 PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
336 PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
337 PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
338 PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
339 PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
340 PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
342 PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
343 PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
344 PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
345 PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
346 PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
347 PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
348 PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
349 PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
351 PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
352 PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
353 PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
355 PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
356 PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
357 PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
358 PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
360 PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
361 PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
362 PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
363 PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
364 PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
365 PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
366 PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
367 PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
369 PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
370 PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
371 PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
372 PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
373 PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
374 PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
375 PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
376 PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
379 PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
380 PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
383 PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
384 PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
385 PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
388 PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
389 PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
390 PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
391 PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
392 PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
393 PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
394 PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
395 PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
397 PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
398 PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
399 PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
400 PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
401 PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
402 PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
403 PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
404 PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
406 PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
407 PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
408 PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
409 PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
410 PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
411 PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
412 PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
413 PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
415 PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
416 PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
417 PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
418 PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
419 PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
420 PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
421 PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
422 PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
425 PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
426 PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
427 PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
428 PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
429 PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
430 PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
431 PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
432 PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
434 PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
436 PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
437 PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
438 PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
439 PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
440 PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
441 PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
443 /* these pin groups only have pullup and pull down control */
444 PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
446 PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
448 PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
450 PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
452 PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
454 PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
456 PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
458 PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
460 PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
464 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
466 struct pmux_tri_ctlr *pmt =
467 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
468 u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
473 reg |= TRISTATE_MASK(pin);
475 reg &= ~TRISTATE_MASK(pin);
479 void pinmux_tristate_enable(enum pmux_pingrp pin)
481 pinmux_set_tristate(pin, 1);
484 void pinmux_tristate_disable(enum pmux_pingrp pin)
486 pinmux_set_tristate(pin, 0);
489 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
491 struct pmux_tri_ctlr *pmt =
492 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
493 enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
494 u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
497 mask_bit = PULL_SHIFT(pull_id);
500 reg &= ~(0x3 << mask_bit);
501 reg |= pupd << mask_bit;
505 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
507 struct pmux_tri_ctlr *pmt =
508 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
509 enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
510 u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
515 assert(pmux_func_isvalid(func));
517 /* Handle special values */
518 if (func >= PMUX_FUNC_RSVD1) {
519 mux = (func - PMUX_FUNC_RSVD1) & 0x3;
521 /* Search for the appropriate function */
522 for (i = 0; i < 4; i++) {
523 if (tegra_soc_pingroups[pin].funcs[i] == func) {
531 mask_bit = MUXCTL_SHIFT(mux_id);
533 reg &= ~(0x3 << mask_bit);
534 reg |= mux << mask_bit;
538 void pinmux_config_pingroup(const struct pingroup_config *config)
540 enum pmux_pingrp pin = config->pingroup;
542 pinmux_set_func(pin, config->func);
543 pinmux_set_pullupdown(pin, config->pull);
544 pinmux_set_tristate(pin, config->tristate);
547 void pinmux_config_table(const struct pingroup_config *config, int len)
551 for (i = 0; i < len; i++)
552 pinmux_config_pingroup(&config[i]);