arch/arm/dts/mx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         tzic: tz-interrupt-controller@0fffc000 {
  32                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  33                 interrupt-controller;
  34                 #interrupt-cells = <1>;
  35                 reg = <0x0fffc000 0x4000>;
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 ckil {
  43                         compatible = "fsl,imx-ckil", "fixed-clock";
  44                         clock-frequency = <32768>;
  45                 };
  46
  47                 ckih1 {
  48                         compatible = "fsl,imx-ckih1", "fixed-clock";
  49                         clock-frequency = <22579200>;
  50                 };
  51
  52                 ckih2 {
  53                         compatible = "fsl,imx-ckih2", "fixed-clock";
  54                         clock-frequency = <0>;
  55                 };
  56
  57                 osc {
  58                         compatible = "fsl,imx-osc", "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61         };
  62
  63         soc {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 compatible = "simple-bus";
  67                 interrupt-parent = <&tzic>;
  68                 ranges;
  69
  70                 extmc@00000000 {
  71                         compatible = "fsl,extmc", "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         reg = <0x00000000 0x40000000>;
  75                         ranges;
  76
  77                         sata@10000000 {
  78                                 compatible = "fsl,imx53-sata", "fsl,imx-ahci";
  79                                 reg = <0x10000000 0x00004000>;
  80                                 interrupts = <28>;
  81                                 status = "disabled";
  82                         };
  83
  84                         ipu@1e000000 {
  85                                 compatible = "fsl,imx-ipuv3";
  86                                 reg = <0x1e000000 0x02000000>;
  87                                 interrupts = <10 11>;
  88                                 status = "disabled";
  89                         };
  90                 };
  91
  92                 aips@50000000 { /* AIPS1 */
  93                         compatible = "fsl,aips-bus", "simple-bus";
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         reg = <0x50000000 0x10000000>;
  97                         ranges;
  98
  99                         spba@50000000 {
 100                                 compatible = "fsl,spba-bus", "simple-bus";
 101                                 #address-cells = <1>;
 102                                 #size-cells = <1>;
 103                                 reg = <0x50000000 0x40000>;
 104                                 ranges;
 105
 106                                 esdhc@50004000 { /* ESDHC1 */
 107                                         compatible = "fsl,imx53-esdhc";
 108                                         reg = <0x50004000 0x4000>;
 109                                         interrupts = <1>;
 110                                         status = "disabled";
 111                                 };
 112
 113                                 esdhc@50008000 { /* ESDHC2 */
 114                                         compatible = "fsl,imx53-esdhc";
 115                                         reg = <0x50008000 0x4000>;
 116                                         interrupts = <2>;
 117                                         status = "disabled";
 118                                 };
 119
 120                                 uart3: serial@5000c000 {
 121                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 122                                         reg = <0x5000c000 0x4000>;
 123                                         interrupts = <33>;
 124                                         status = "disabled";
 125                                 };
 126
 127                                 ecspi@50010000 { /* ECSPI1 */
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 131                                         reg = <0x50010000 0x4000>;
 132                                         interrupts = <36>;
 133                                         status = "disabled";
 134                                 };
 135
 136                                 ssi2: ssi@50014000 {
 137                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 138                                         reg = <0x50014000 0x4000>;
 139                                         interrupts = <30>;
 140                                         fsl,fifo-depth = <15>;
 141                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 142                                         status = "disabled";
 143                                 };
 144
 145                                 esdhc@50020000 { /* ESDHC3 */
 146                                         compatible = "fsl,imx53-esdhc";
 147                                         reg = <0x50020000 0x4000>;
 148                                         interrupts = <3>;
 149                                         status = "disabled";
 150                                 };
 151
 152                                 esdhc@50024000 { /* ESDHC4 */
 153                                         compatible = "fsl,imx53-esdhc";
 154                                         reg = <0x50024000 0x4000>;
 155                                         interrupts = <4>;
 156                                         status = "disabled";
 157                                 };
 158                         };
 159
 160                         usb@53f80000 {
 161                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 162                                 reg = <0x53f80000 0x0200>;
 163                                 interrupts = <18>;
 164                                 status = "disabled";
 165                         };
 166
 167                         usb@53f80200 {
 168                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 169                                 reg = <0x53f80200 0x0200>;
 170                                 interrupts = <14>;
 171                                 status = "disabled";
 172                         };
 173
 174                         usb@53f80400 {
 175                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 176                                 reg = <0x53f80400 0x0200>;
 177                                 interrupts = <16>;
 178                                 status = "disabled";
 179                         };
 180
 181                         usb@53f80600 {
 182                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 183                                 reg = <0x53f80600 0x0200>;
 184                                 interrupts = <17>;
 185                                 status = "disabled";
 186                         };
 187
 188                         gpio1: gpio@53f84000 {
 189                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 190                                 reg = <0x53f84000 0x4000>;
 191                                 interrupts = <50 51>;
 192                                 gpio-controller;
 193                                 #gpio-cells = <2>;
 194                                 interrupt-controller;
 195                                 #interrupt-cells = <2>;
 196                         };
 197
 198                         gpio2: gpio@53f88000 {
 199                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 200                                 reg = <0x53f88000 0x4000>;
 201                                 interrupts = <52 53>;
 202                                 gpio-controller;
 203                                 #gpio-cells = <2>;
 204                                 interrupt-controller;
 205                                 #interrupt-cells = <2>;
 206                         };
 207
 208                         gpio3: gpio@53f8c000 {
 209                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 210                                 reg = <0x53f8c000 0x4000>;
 211                                 interrupts = <54 55>;
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 interrupt-controller;
 215                                 #interrupt-cells = <2>;
 216                         };
 217
 218                         gpio4: gpio@53f90000 {
 219                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 220                                 reg = <0x53f90000 0x4000>;
 221                                 interrupts = <56 57>;
 222                                 gpio-controller;
 223                                 #gpio-cells = <2>;
 224                                 interrupt-controller;
 225                                 #interrupt-cells = <2>;
 226                         };
 227
 228                         keypad@53f94000 {
 229                                 compatible = "fsl,imx-keypad";
 230                                 reg = <0x53f94000 0x4000>;
 231                                 interrupts = <60>;
 232                                 status = "disabled";
 233                         };
 234
 235                         wdog@53f98000 { /* WDOG1 */
 236                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 237                                 reg = <0x53f98000 0x4000>;
 238                                 interrupts = <58>;
 239                                 status = "disabled";
 240                         };
 241
 242                         wdog@53f9c000 { /* WDOG2 */
 243                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 244                                 reg = <0x53f9c000 0x4000>;
 245                                 interrupts = <59>;
 246                                 status = "disabled";
 247                         };
 248
 249                         iomuxc@53fa8000 {
 250                                 compatible = "fsl,imx53-iomuxc";
 251                                 reg = <0x53fa8000 0x4000>;
 252
 253                                 audmux {
 254                                         pinctrl_audmux_1: audmuxgrp-1 {
 255                                                 fsl,pins = <
 256                                                         10 0x80 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
 257                                                         17 0x80 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
 258                                                         23 0x80 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
 259                                                         30 0x80 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
 260                                                 >;
 261                                         };
 262                                 };
 263
 264                                 fec {
 265                                         pinctrl_fec_1: fecgrp-1 {
 266                                                 fsl,pins = <
 267                                                         820 0x80        /* MX53_PAD_FEC_MDC__FEC_MDC */
 268                                                         779 0x80        /* MX53_PAD_FEC_MDIO__FEC_MDIO */
 269                                                         786 0x80        /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
 270                                                         791 0x80        /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
 271                                                         796 0x80        /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
 272                                                         799 0x80        /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
 273                                                         804 0x80        /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
 274                                                         808 0x80        /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
 275                                                         811 0x80        /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
 276                                                         816 0x80        /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
 277                                                 >;
 278                                         };
 279                                 };
 280
 281                                 ecspi1 {
 282                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 283                                                 fsl,pins = <
 284                                                         433 0x80        /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
 285                                                         439 0x80        /* MX53_PAD_EIM_D17__ECSPI1_MISO */
 286                                                         445 0x80        /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
 287                                                 >;
 288                                         };
 289                                 };
 290
 291                                 esdhc1 {
 292                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 293                                                 fsl,pins = <
 294                                                         995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
 295                                                         1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
 296                                                         1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
 297                                                         1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
 298                                                         1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
 299                                                         1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 300                                                 >;
 301                                         };
 302
 303                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 304                                                 fsl,pins = <
 305                                                         995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
 306                                                         1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
 307                                                         1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
 308                                                         1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
 309                                                         941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
 310                                                         948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
 311                                                         955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
 312                                                         962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
 313                                                         1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
 314                                                         1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 315                                                 >;
 316                                         };
 317                                 };
 318
 319                                 esdhc2 {
 320                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 321                                                 fsl,pins = <
 322                                                         1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
 323                                                         1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
 324                                                         1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
 325                                                         1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
 326                                                         1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
 327                                                         1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
 328                                                 >;
 329                                         };
 330                                 };
 331
 332                                 esdhc3 {
 333                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 334                                                 fsl,pins = <
 335                                                         943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
 336                                                         950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
 337                                                         957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
 338                                                         964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
 339                                                         893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
 340                                                         900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
 341                                                         906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
 342                                                         912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
 343                                                         857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
 344                                                         863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
 345                                                 >;
 346                                         };
 347                                 };
 348
 349                                 i2c1 {
 350                                         pinctrl_i2c1_1: i2c1grp-1 {
 351                                                 fsl,pins = <
 352                                                         333 0xc0        /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
 353                                                         341 0xc0        /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
 354                                                 >;
 355                                         };
 356
 357                                         pinctrl_i2c1_2: i2c1grp-2 {
 358                                                 fsl,pins = <
 359                                                         529 0xc0        /* MX53_PAD_EIM_D28__I2C1_SDA */
 360                                                         469 0xc0        /* MX53_PAD_EIM_D21__I2C1_SCL */
 361                                                 >;
 362                                         };
 363                                 };
 364
 365                                 i2c2 {
 366                                         pinctrl_i2c2_1: i2c2grp-1 {
 367                                                 fsl,pins = <
 368                                                         61 0xc0         /* MX53_PAD_KEY_ROW3__I2C2_SDA */
 369                                                         53 0xc0         /* MX53_PAD_KEY_COL3__I2C2_SCL */
 370                                                 >;
 371                                         };
 372                                 };
 373
 374                                 i2c3 {
 375                                         pinctrl_i2c3_1: i2c3grp-1 {
 376                                                 fsl,pins = <
 377                                                         1102 0xc0       /* MX53_PAD_GPIO_6__I2C3_SDA */
 378                                                         1094 0xc0       /* MX53_PAD_GPIO_3__I2C3_SCL */
 379                                                 >;
 380                                         };
 381                                 };
 382
 383                                 uart1 {
 384                                         pinctrl_uart1_1: uart1grp-1 {
 385                                                 fsl,pins = <
 386                                                         346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
 387                                                         354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
 388                                                 >;
 389                                         };
 390
 391                                         pinctrl_uart1_2: uart1grp-2 {
 392                                                 fsl,pins = <
 393                                                         828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
 394                                                         832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
 395                                                 >;
 396                                         };
 397                                 };
 398
 399                                 uart2 {
 400                                         pinctrl_uart2_1: uart2grp-1 {
 401                                                 fsl,pins = <
 402                                                         841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
 403                                                         836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
 404                                                 >;
 405                                         };
 406                                 };
 407
 408                                 uart3 {
 409                                         pinctrl_uart3_1: uart3grp-1 {
 410                                                 fsl,pins = <
 411                                                         884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
 412                                                         888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
 413                                                         875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
 414                                                         880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
 415                                                 >;
 416                                         };
 417                                 };
 418                         };
 419                         pwm@53fb4000 {
 420                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 421                                 reg = <0x53fb4000 0x4000>;
 422                                 interrupts = <61>;
 423                                 status = "disabled";
 424                         };
 425
 426                         pwm@53fb8000 {
 427                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 428                                 reg = <0x53fb8000 0x4000>;
 429                                 interrupts = <94>;
 430                                 status = "disabled";
 431                         };
 432
 433                         uart1: serial@53fbc000 {
 434                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 435                                 reg = <0x53fbc000 0x4000>;
 436                                 interrupts = <31>;
 437                                 status = "disabled";
 438                         };
 439
 440                         uart2: serial@53fc0000 {
 441                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 442                                 reg = <0x53fc0000 0x4000>;
 443                                 interrupts = <32>;
 444                                 status = "disabled";
 445                         };
 446
 447                         can1: can@53fc8000 {
 448                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 449                                 reg = <0x53fc8000 0x4000>;
 450                                 interrupts = <82>;
 451                                 status = "disabled";
 452                         };
 453
 454                         can2: can@53fcc000 {
 455                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 456                                 reg = <0x53fcc000 0x4000>;
 457                                 interrupts = <83>;
 458                                 status = "disabled";
 459                         };
 460
 461                         gpio5: gpio@53fdc000 {
 462                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 463                                 reg = <0x53fdc000 0x4000>;
 464                                 interrupts = <103 104>;
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <2>;
 469                         };
 470
 471                         gpio6: gpio@53fe0000 {
 472                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 473                                 reg = <0x53fe0000 0x4000>;
 474                                 interrupts = <105 106>;
 475                                 gpio-controller;
 476                                 #gpio-cells = <2>;
 477                                 interrupt-controller;
 478                                 #interrupt-cells = <2>;
 479                         };
 480
 481                         gpio7: gpio@53fe4000 {
 482                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 483                                 reg = <0x53fe4000 0x4000>;
 484                                 interrupts = <107 108>;
 485                                 gpio-controller;
 486                                 #gpio-cells = <2>;
 487                                 interrupt-controller;
 488                                 #interrupt-cells = <2>;
 489                         };
 490
 491                         i2c@53fec000 { /* I2C3 */
 492                                 #address-cells = <1>;
 493                                 #size-cells = <0>;
 494                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
 495                                 reg = <0x53fec000 0x4000>;
 496                                 interrupts = <64>;
 497                                 status = "disabled";
 498                         };
 499
 500                         uart4: serial@53ff0000 {
 501                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 502                                 reg = <0x53ff0000 0x4000>;
 503                                 interrupts = <13>;
 504                                 status = "disabled";
 505                         };
 506                 };
 507
 508                 aips@60000000 { /* AIPS2 */
 509                         compatible = "fsl,aips-bus", "simple-bus";
 510                         #address-cells = <1>;
 511                         #size-cells = <1>;
 512                         reg = <0x60000000 0x10000000>;
 513                         ranges;
 514
 515                         uart5: serial@63f90000 {
 516                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 517                                 reg = <0x63f90000 0x4000>;
 518                                 interrupts = <86>;
 519                                 status = "disabled";
 520                         };
 521
 522                         ecspi@63fac000 { /* ECSPI2 */
 523                                 #address-cells = <1>;
 524                                 #size-cells = <0>;
 525                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 526                                 reg = <0x63fac000 0x4000>;
 527                                 interrupts = <37>;
 528                                 status = "disabled";
 529                         };
 530
 531                         sdma@63fb0000 {
 532                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 533                                 reg = <0x63fb0000 0x4000>;
 534                                 interrupts = <6>;
 535                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 536                         };
 537
 538                         cspi@63fc0000 {
 539                                 #address-cells = <1>;
 540                                 #size-cells = <0>;
 541                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 542                                 reg = <0x63fc0000 0x4000>;
 543                                 interrupts = <38>;
 544                                 status = "disabled";
 545                         };
 546
 547                         i2c@63fc4000 { /* I2C2 */
 548                                 #address-cells = <1>;
 549                                 #size-cells = <0>;
 550                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
 551                                 reg = <0x63fc4000 0x4000>;
 552                                 interrupts = <63>;
 553                                 status = "disabled";
 554                         };
 555
 556                         i2c@63fc8000 { /* I2C1 */
 557                                 #address-cells = <1>;
 558                                 #size-cells = <0>;
 559                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
 560                                 reg = <0x63fc8000 0x4000>;
 561                                 interrupts = <62>;
 562                                 status = "disabled";
 563                         };
 564
 565                         ssi1: ssi@63fcc000 {
 566                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 567                                 reg = <0x63fcc000 0x4000>;
 568                                 interrupts = <29>;
 569                                 fsl,fifo-depth = <15>;
 570                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 571                                 status = "disabled";
 572                         };
 573
 574                         audmux@63fd0000 {
 575                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 576                                 reg = <0x63fd0000 0x4000>;
 577                                 status = "disabled";
 578                         };
 579
 580                         nand@63fdb000 {
 581                                 compatible = "fsl,imx53-nand";
 582                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 583                                 interrupts = <8>;
 584                                 status = "disabled";
 585                         };
 586
 587                         ssi3: ssi@63fe8000 {
 588                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 589                                 reg = <0x63fe8000 0x4000>;
 590                                 interrupts = <96>;
 591                                 fsl,fifo-depth = <15>;
 592                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 593                                 status = "disabled";
 594                         };
 595
 596                         ethernet@63fec000 {
 597                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 598                                 reg = <0x63fec000 0x4000>;
 599                                 interrupts = <87>;
 600                                 status = "disabled";
 601                         };
 602                 };
 603         };
 604 };