arch/arm/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         tegra_car: clock@60006000 {
   8                 compatible = "nvidia,tegra20-car";
   9                 reg = <0x60006000 0x1000>;
  10                 #clock-cells = <1>;
  11         };
  12
  13         intc: interrupt-controller@50041000 {
  14                 compatible = "nvidia,tegra20-gic";
  15                 interrupt-controller;
  16                 #interrupt-cells = <1>;
  17                 reg = < 0x50041000 0x1000 >,
  18                       < 0x50040100 0x0100 >;
  19         };
  20
  21         i2c@7000c000 {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 compatible = "nvidia,tegra20-i2c";
  25                 reg = <0x7000C000 0x100>;
  26                 interrupts = < 70 >;
  27                 /* PERIPH_ID_I2C1, PLL_P_OUT3 */
  28                 clocks = <&tegra_car 12>, <&tegra_car 124>;
  29         };
  30
  31         i2c@7000c400 {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 compatible = "nvidia,tegra20-i2c";
  35                 reg = <0x7000C400 0x100>;
  36                 interrupts = < 116 >;
  37                 /* PERIPH_ID_I2C2, PLL_P_OUT3 */
  38                 clocks = <&tegra_car 54>, <&tegra_car 124>;
  39         };
  40
  41         i2c@7000c500 {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44                 compatible = "nvidia,tegra20-i2c";
  45                 reg = <0x7000C500 0x100>;
  46                 interrupts = < 124 >;
  47                 /* PERIPH_ID_I2C3, PLL_P_OUT3 */
  48                 clocks = <&tegra_car 67>, <&tegra_car 124>;
  49         };
  50
  51         i2c@7000d000 {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 compatible = "nvidia,tegra20-i2c-dvc";
  55                 reg = <0x7000D000 0x200>;
  56                 interrupts = < 85 >;
  57                 /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
  58                 clocks = <&tegra_car 47>, <&tegra_car 124>;
  59         };
  60
  61         i2s@70002800 {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64                 compatible = "nvidia,tegra20-i2s";
  65                 reg = <0x70002800 0x200>;
  66                 interrupts = < 45 >;
  67                 dma-channel = < 2 >;
  68         };
  69
  70         i2s@70002a00 {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 compatible = "nvidia,tegra20-i2s";
  74                 reg = <0x70002a00 0x200>;
  75                 interrupts = < 35 >;
  76                 dma-channel = < 1 >;
  77         };
  78
  79         das@70000c00 {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82                 compatible = "nvidia,tegra20-das";
  83                 reg = <0x70000c00 0x80>;
  84         };
  85
  86         gpio: gpio@6000d000 {
  87                 compatible = "nvidia,tegra20-gpio";
  88                 reg = < 0x6000d000 0x1000 >;
  89                 interrupts = < 64 65 66 67 87 119 121 >;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92         };
  93
  94         pinmux: pinmux@70000000 {
  95                 compatible = "nvidia,tegra20-pinmux";
  96                 reg = < 0x70000014 0x10    /* Tri-state registers */
  97                         0x70000080 0x20    /* Mux registers */
  98                         0x700000a0 0x14    /* Pull-up/down registers */
  99                         0x70000868 0xa8 >; /* Pad control registers */
 100         };
 101
 102         serial@70006000 {
 103                 compatible = "nvidia,tegra20-uart";
 104                 reg = <0x70006000 0x40>;
 105                 reg-shift = <2>;
 106                 interrupts = < 68 >;
 107         };
 108
 109         serial@70006040 {
 110                 compatible = "nvidia,tegra20-uart";
 111                 reg = <0x70006040 0x40>;
 112                 reg-shift = <2>;
 113                 interrupts = < 69 >;
 114         };
 115
 116         serial@70006200 {
 117                 compatible = "nvidia,tegra20-uart";
 118                 reg = <0x70006200 0x100>;
 119                 reg-shift = <2>;
 120                 interrupts = < 78 >;
 121         };
 122
 123         serial@70006300 {
 124                 compatible = "nvidia,tegra20-uart";
 125                 reg = <0x70006300 0x100>;
 126                 reg-shift = <2>;
 127                 interrupts = < 122 >;
 128         };
 129
 130         serial@70006400 {
 131                 compatible = "nvidia,tegra20-uart";
 132                 reg = <0x70006400 0x100>;
 133                 reg-shift = <2>;
 134                 interrupts = < 123 >;
 135         };
 136
 137         sdhci@c8000000 {
 138                 compatible = "nvidia,tegra20-sdhci";
 139                 reg = <0xc8000000 0x200>;
 140                 interrupts = < 46 >;
 141         };
 142
 143         sdhci@c8000200 {
 144                 compatible = "nvidia,tegra20-sdhci";
 145                 reg = <0xc8000200 0x200>;
 146                 interrupts = < 47 >;
 147         };
 148
 149         sdhci@c8000400 {
 150                 compatible = "nvidia,tegra20-sdhci";
 151                 reg = <0xc8000400 0x200>;
 152                 interrupts = < 51 >;
 153         };
 154
 155         sdhci@c8000600 {
 156                 compatible = "nvidia,tegra20-sdhci";
 157                 reg = <0xc8000600 0x200>;
 158                 interrupts = < 63 >;
 159         };
 160
 161         usb@c5000000 {
 162                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 163                 reg = <0xc5000000 0x4000>;
 164                 interrupts = < 52 >;
 165                 phy_type = "utmi";
 166                 clocks = <&tegra_car 22>;       /* PERIPH_ID_USBD */
 167                 nvidia,has-legacy-mode;
 168         };
 169
 170         usb@c5004000 {
 171                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 172                 reg = <0xc5004000 0x4000>;
 173                 interrupts = < 53 >;
 174                 phy_type = "ulpi";
 175                 clocks = <&tegra_car 58>;       /* PERIPH_ID_USB2 */
 176         };
 177
 178         usb@c5008000 {
 179                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 180                 reg = <0xc5008000 0x4000>;
 181                 interrupts = < 129 >;
 182                 phy_type = "utmi";
 183                 clocks = <&tegra_car 59>;       /* PERIPH_ID_USB3 */
 184         };
 185
 186         emc@7000f400 {
 187                 #address-cells = < 1 >;
 188                 #size-cells = < 0 >;
 189                 compatible = "nvidia,tegra20-emc";
 190                 reg = <0x7000f400 0x200>;
 191         };
 192
 193         kbc@7000e200 {
 194                 compatible = "nvidia,tegra20-kbc";
 195                 reg = <0x7000e200 0x0078>;
 196         };
 197
 198         nand: nand-controller@70008000 {
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 compatible = "nvidia,tegra20-nand";
 202                 reg = <0x70008000 0x100>;
 203         };
 204
 205         pwm: pwm@7000a000 {
 206                 compatible = "nvidia,tegra20-pwm";
 207                 reg = <0x7000a000 0x100>;
 208                 #pwm-cells = <2>;
 209         };
 210
 211         host1x {
 212                 compatible = "nvidia,tegra20-host1x", "simple-bus";
 213                 reg = <0x50000000 0x00024000>;
 214                 interrupts = <0 65 0x04   /* mpcore syncpt */
 215                               0 67 0x04>; /* mpcore general */
 216                 status = "disabled";
 217
 218                 #address-cells = <1>;
 219                 #size-cells = <1>;
 220
 221                 ranges = <0x54000000 0x54000000 0x04000000>;
 222
 223                 /* video-encoding/decoding */
 224                 mpe {
 225                         reg = <0x54040000 0x00040000>;
 226                         interrupts = <0 68 0x04>;
 227                         status = "disabled";
 228                 };
 229
 230                 /* video input */
 231                 vi {
 232                         reg = <0x54080000 0x00040000>;
 233                         interrupts = <0 69 0x04>;
 234                         status = "disabled";
 235                 };
 236
 237                 /* EPP */
 238                 epp {
 239                         reg = <0x540c0000 0x00040000>;
 240                         interrupts = <0 70 0x04>;
 241                         status = "disabled";
 242                 };
 243
 244                 /* ISP */
 245                 isp {
 246                         reg = <0x54100000 0x00040000>;
 247                         interrupts = <0 71 0x04>;
 248                         status = "disabled";
 249                 };
 250
 251                 /* 2D engine */
 252                 gr2d {
 253                         reg = <0x54140000 0x00040000>;
 254                         interrupts = <0 72 0x04>;
 255                         status = "disabled";
 256                 };
 257
 258                 /* 3D engine */
 259                 gr3d {
 260                         reg = <0x54180000 0x00040000>;
 261                         status = "disabled";
 262                 };
 263
 264                 /* display controllers */
 265                 dc@54200000 {
 266                         compatible = "nvidia,tegra20-dc";
 267                         reg = <0x54200000 0x00040000>;
 268                         interrupts = <0 73 0x04>;
 269                         status = "disabled";
 270
 271                         rgb {
 272                                 status = "disabled";
 273                         };
 274                 };
 275
 276                 dc@54240000 {
 277                         compatible = "nvidia,tegra20-dc";
 278                         reg = <0x54240000 0x00040000>;
 279                         interrupts = <0 74 0x04>;
 280                         status = "disabled";
 281
 282                         rgb {
 283                                 status = "disabled";
 284                         };
 285                 };
 286
 287                 /* outputs */
 288                 hdmi {
 289                         compatible = "nvidia,tegra20-hdmi";
 290                         reg = <0x54280000 0x00040000>;
 291                         interrupts = <0 75 0x04>;
 292                         status = "disabled";
 293                 };
 294
 295                 tvo {
 296                         compatible = "nvidia,tegra20-tvo";
 297                         reg = <0x542c0000 0x00040000>;
 298                         interrupts = <0 76 0x04>;
 299                         status = "disabled";
 300                 };
 301
 302                 dsi {
 303                         compatible = "nvidia,tegra20-dsi";
 304                         reg = <0x54300000 0x00040000>;
 305                         status = "disabled";
 306                 };
 307         };
 308
 309 };