arch/arm/dts/uniphier-ph1-sld8.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD8 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld8";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a9";
  21                         reg = <0>;
  22                 };
  23         };
  24
  25         clocks {
  26                 arm_timer_clk: arm_timer_clk {
  27                         #clock-cells = <0>;
  28                         compatible = "fixed-clock";
  29                         clock-frequency = <50000000>;
  30                 };
  31         };
  32
  33         soc {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges;
  38                 interrupt-parent = <&intc>;
  39
  40                 extbus: extbus {
  41                         compatible = "simple-bus";
  42                         #address-cells = <2>;
  43                         #size-cells = <1>;
  44                 };
  45
  46                 uart0: serial@54006800 {
  47                         compatible = "socionext,uniphier-uart";
  48                         status = "disabled";
  49                         reg = <0x54006800 0x20>;
  50                         clock-frequency = <80000000>;
  51                 };
  52
  53                 uart1: serial@54006900 {
  54                         compatible = "socionext,uniphier-uart";
  55                         status = "disabled";
  56                         reg = <0x54006900 0x20>;
  57                         clock-frequency = <80000000>;
  58                 };
  59
  60                 uart2: serial@54006a00 {
  61                         compatible = "socionext,uniphier-uart";
  62                         status = "disabled";
  63                         reg = <0x54006a00 0x20>;
  64                         clock-frequency = <80000000>;
  65                 };
  66
  67                 uart3: serial@54006b00 {
  68                         compatible = "socionext,uniphier-uart";
  69                         status = "disabled";
  70                         reg = <0x54006b00 0x20>;
  71                         clock-frequency = <80000000>;
  72                 };
  73
  74                 i2c0: i2c@58400000 {
  75                         compatible = "socionext,uniphier-i2c";
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         reg = <0x58400000 0x40>;
  79                         clock-frequency = <100000>;
  80                         status = "disabled";
  81                 };
  82
  83                 i2c1: i2c@58480000 {
  84                         compatible = "socionext,uniphier-i2c";
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87                         reg = <0x58480000 0x40>;
  88                         clock-frequency = <100000>;
  89                         status = "disabled";
  90                 };
  91
  92                 i2c2: i2c@58500000 {
  93                         compatible = "socionext,uniphier-i2c";
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96                         reg = <0x58500000 0x40>;
  97                         clock-frequency = <100000>;
  98                         status = "disabled";
  99                 };
 100
 101                 i2c3: i2c@58580000 {
 102                         compatible = "socionext,uniphier-i2c";
 103                         #address-cells = <1>;
 104                         #size-cells = <0>;
 105                         reg = <0x58580000 0x40>;
 106                         clock-frequency = <100000>;
 107                         status = "disabled";
 108                 };
 109
 110                 system-bus-controller-misc@59800000 {
 111                         compatible = "socionext,uniphier-system-bus-controller-misc",
 112                                      "syscon";
 113                         reg = <0x59800000 0x2000>;
 114                 };
 115
 116                 usb0: usb@5a800100 {
 117                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 118                         status = "disabled";
 119                         reg = <0x5a800100 0x100>;
 120                 };
 121
 122                 usb1: usb@5a810100 {
 123                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 124                         status = "disabled";
 125                         reg = <0x5a810100 0x100>;
 126                 };
 127
 128                 usb2: usb@5a820100 {
 129                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 130                         status = "disabled";
 131                         reg = <0x5a820100 0x100>;
 132                 };
 133
 134                 timer@60000200 {
 135                         compatible = "arm,cortex-a9-global-timer";
 136                         reg = <0x60000200 0x20>;
 137                         interrupts = <1 11 0x104>;
 138                         clocks = <&arm_timer_clk>;
 139                 };
 140
 141                 timer@60000600 {
 142                         compatible = "arm,cortex-a9-twd-timer";
 143                         reg = <0x60000600 0x20>;
 144                         interrupts = <1 13 0x104>;
 145                         clocks = <&arm_timer_clk>;
 146                 };
 147
 148                 intc: interrupt-controller@60001000 {
 149                         compatible = "arm,cortex-a9-gic";
 150                         #interrupt-cells = <3>;
 151                         interrupt-controller;
 152                         reg = <0x60001000 0x1000>,
 153                               <0x60000100 0x100>;
 154                 };
 155
 156                 nand: nand@68000000 {
 157                         compatible = "denali,denali-nand-dt";
 158                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 159                         reg-names = "nand_data", "denali_reg";
 160                 };
 161         };
 162 };