arch/arm/include/asm/arch-exynos/cpu.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  */
  21
  22 #ifndef _EXYNOS4_CPU_H
  23 #define _EXYNOS4_CPU_H
  24
  25 #define DEVICE_NOT_AVAILABLE            0
  26
  27 #define EXYNOS_CPU_NAME                 "Exynos"
  28 #define EXYNOS4_ADDR_BASE               0x10000000
  29
  30 /* EXYNOS4 Common*/
  31 #define EXYNOS4_I2C_SPACING             0x10000
  32
  33 #define EXYNOS4_GPIO_PART3_BASE         0x03860000
  34 #define EXYNOS4_PRO_ID                  0x10000000
  35 #define EXYNOS4_SYSREG_BASE             0x10010000
  36 #define EXYNOS4_POWER_BASE              0x10020000
  37 #define EXYNOS4_SWRESET                 0x10020400
  38 #define EXYNOS4_CLOCK_BASE              0x10030000
  39 #define EXYNOS4_SYSTIMER_BASE           0x10050000
  40 #define EXYNOS4_WATCHDOG_BASE           0x10060000
  41 #define EXYNOS4_TZPC_BASE               0x10110000
  42 #define EXYNOS4_MIU_BASE                0x10600000
  43 #define EXYNOS4_DMC0_BASE               0x10400000
  44 #define EXYNOS4_DMC1_BASE               0x10410000
  45 #define EXYNOS4_GPIO_PART2_BASE         0x11000000
  46 #define EXYNOS4_GPIO_PART1_BASE         0x11400000
  47 #define EXYNOS4_FIMD_BASE               0x11C00000
  48 #define EXYNOS4_MIPI_DSIM_BASE          0x11C80000
  49 #define EXYNOS4_USBOTG_BASE             0x12480000
  50 #define EXYNOS4_MMC_BASE                0x12510000
  51 #define EXYNOS4_SROMC_BASE              0x12570000
  52 #define EXYNOS4_USB_HOST_EHCI_BASE      0x12580000
  53 #define EXYNOS4_USBPHY_BASE             0x125B0000
  54 #define EXYNOS4_UART_BASE               0x13800000
  55 #define EXYNOS4_I2C_BASE                0x13860000
  56 #define EXYNOS4_ADC_BASE                0x13910000
  57 #define EXYNOS4_SPI_BASE                0x13920000
  58 #define EXYNOS4_PWMTIMER_BASE           0x139D0000
  59 #define EXYNOS4_MODEM_BASE              0x13A00000
  60 #define EXYNOS4_USBPHY_CONTROL          0x10020704
  61 #define EXYNOS4_I2S_BASE                0xE2100000
  62
  63 #define EXYNOS4_GPIO_PART4_BASE         DEVICE_NOT_AVAILABLE
  64 #define EXYNOS4_DP_BASE                 DEVICE_NOT_AVAILABLE
  65 #define EXYNOS4_SPI_ISP_BASE            DEVICE_NOT_AVAILABLE
  66 #define EXYNOS4_ACE_SFR_BASE            DEVICE_NOT_AVAILABLE
  67
  68 /* EXYNOS4X12 */
  69 #define EXYNOS4X12_GPIO_PART3_BASE      0x03860000
  70 #define EXYNOS4X12_PRO_ID               0x10000000
  71 #define EXYNOS4X12_SYSREG_BASE          0x10010000
  72 #define EXYNOS4X12_POWER_BASE           0x10020000
  73 #define EXYNOS4X12_SWRESET              0x10020400
  74 #define EXYNOS4X12_USBPHY_CONTROL       0x10020704
  75 #define EXYNOS4X12_CLOCK_BASE           0x10030000
  76 #define EXYNOS4X12_SYSTIMER_BASE        0x10050000
  77 #define EXYNOS4X12_WATCHDOG_BASE        0x10060000
  78 #define EXYNOS4X12_TZPC_BASE            0x10110000
  79 #define EXYNOS4X12_DMC0_BASE            0x10600000
  80 #define EXYNOS4X12_DMC1_BASE            0x10610000
  81 #define EXYNOS4X12_GPIO_PART4_BASE      0x106E0000
  82 #define EXYNOS4X12_GPIO_PART2_BASE      0x11000000
  83 #define EXYNOS4X12_GPIO_PART1_BASE      0x11400000
  84 #define EXYNOS4X12_FIMD_BASE            0x11C00000
  85 #define EXYNOS4X12_MIPI_DSIM_BASE       0x11C80000
  86 #define EXYNOS4X12_USBOTG_BASE          0x12480000
  87 #define EXYNOS4X12_MMC_BASE             0x12510000
  88 #define EXYNOS4X12_SROMC_BASE           0x12570000
  89 #define EXYNOS4X12_USB_HOST_EHCI_BASE   0x12580000
  90 #define EXYNOS4X12_USBPHY_BASE          0x125B0000
  91 #define EXYNOS4X12_UART_BASE            0x13800000
  92 #define EXYNOS4X12_I2C_BASE             0x13860000
  93 #define EXYNOS4X12_PWMTIMER_BASE        0x139D0000
  94
  95 #define EXYNOS4X12_ADC_BASE             DEVICE_NOT_AVAILABLE
  96 #define EXYNOS4X12_DP_BASE              DEVICE_NOT_AVAILABLE
  97 #define EXYNOS4X12_MODEM_BASE           DEVICE_NOT_AVAILABLE
  98 #define EXYNOS4X12_I2S_BASE             DEVICE_NOT_AVAILABLE
  99 #define EXYNOS4X12_SPI_BASE             DEVICE_NOT_AVAILABLE
 100 #define EXYNOS4X12_SPI_ISP_BASE         DEVICE_NOT_AVAILABLE
 101 #define EXYNOS4X12_ACE_SFR_BASE         DEVICE_NOT_AVAILABLE
 102
 103 /* EXYNOS5 Common*/
 104 #define EXYNOS5_I2C_SPACING             0x10000
 105
 106 #define EXYNOS5_GPIO_PART4_BASE         0x03860000
 107 #define EXYNOS5_PRO_ID                  0x10000000
 108 #define EXYNOS5_CLOCK_BASE              0x10010000
 109 #define EXYNOS5_POWER_BASE              0x10040000
 110 #define EXYNOS5_SWRESET                 0x10040400
 111 #define EXYNOS5_SYSREG_BASE             0x10050000
 112 #define EXYNOS5_TZPC_BASE               0x10100000
 113 #define EXYNOS5_WATCHDOG_BASE           0x101D0000
 114 #define EXYNOS5_ACE_SFR_BASE            0x10830000
 115 #define EXYNOS5_DMC_PHY0_BASE           0x10C00000
 116 #define EXYNOS5_DMC_PHY1_BASE           0x10C10000
 117 #define EXYNOS5_GPIO_PART3_BASE         0x10D10000
 118 #define EXYNOS5_DMC_CTRL_BASE           0x10DD0000
 119 #define EXYNOS5_GPIO_PART1_BASE         0x11400000
 120 #define EXYNOS5_MIPI_DSIM_BASE          0x11D00000
 121 #define EXYNOS5_USB_HOST_EHCI_BASE      0x12110000
 122 #define EXYNOS5_USBPHY_BASE             0x12130000
 123 #define EXYNOS5_USBOTG_BASE             0x12140000
 124 #define EXYNOS5_MMC_BASE                0x12200000
 125 #define EXYNOS5_SROMC_BASE              0x12250000
 126 #define EXYNOS5_UART_BASE               0x12C00000
 127 #define EXYNOS5_I2C_BASE                0x12C60000
 128 #define EXYNOS5_SPI_BASE                0x12D20000
 129 #define EXYNOS5_I2S_BASE                0x12D60000
 130 #define EXYNOS5_PWMTIMER_BASE           0x12DD0000
 131 #define EXYNOS5_SPI_ISP_BASE            0x131A0000
 132 #define EXYNOS5_GPIO_PART2_BASE         0x13400000
 133 #define EXYNOS5_FIMD_BASE               0x14400000
 134 #define EXYNOS5_DP_BASE                 0x145B0000
 135
 136 #define EXYNOS5_ADC_BASE                DEVICE_NOT_AVAILABLE
 137 #define EXYNOS5_MODEM_BASE              DEVICE_NOT_AVAILABLE
 138
 139 #ifndef __ASSEMBLY__
 140 #include <asm/io.h>
 141 /* CPU detection macros */
 142 extern unsigned int s5p_cpu_id;
 143 extern unsigned int s5p_cpu_rev;
 144
 145 static inline int s5p_get_cpu_rev(void)
 146 {
 147         return s5p_cpu_rev;
 148 }
 149
 150 static inline void s5p_set_cpu_id(void)
 151 {
 152         unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
 153
 154         switch (pro_id) {
 155         case 0x200:
 156                 /* Exynos4210 EVT0 */
 157                 s5p_cpu_id = 0x4210;
 158                 s5p_cpu_rev = 0;
 159                 break;
 160         case 0x210:
 161                 /* Exynos4210 EVT1 */
 162                 s5p_cpu_id = 0x4210;
 163                 break;
 164         case 0x412:
 165                 /* Exynos4412 */
 166                 s5p_cpu_id = 0x4412;
 167                 break;
 168         case 0x520:
 169                 /* Exynos5250 */
 170                 s5p_cpu_id = 0x5250;
 171                 break;
 172         }
 173 }
 174
 175 static inline char *s5p_get_cpu_name(void)
 176 {
 177         return EXYNOS_CPU_NAME;
 178 }
 179
 180 #define IS_SAMSUNG_TYPE(type, id)                       \
 181 static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
 182 {                                                       \
 183         return (s5p_cpu_id >> 12) == id;                \
 184 }
 185
 186 IS_SAMSUNG_TYPE(exynos4, 0x4)
 187 IS_SAMSUNG_TYPE(exynos5, 0x5)
 188
 189 #define IS_EXYNOS_TYPE(type, id)                        \
 190 static inline int __attribute__((no_instrument_function)) \
 191         proid_is_##type(void)                           \
 192 {                                                       \
 193         return s5p_cpu_id == id;                        \
 194 }
 195
 196 IS_EXYNOS_TYPE(exynos4210, 0x4210)
 197 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 198 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 199
 200 #define SAMSUNG_BASE(device, base)                              \
 201 static inline unsigned int __attribute__((no_instrument_function)) \
 202         samsung_get_base_##device(void) \
 203 {                                                               \
 204         if (cpu_is_exynos4()) {                         \
 205                 if (proid_is_exynos4412())                      \
 206                         return EXYNOS4X12_##base;               \
 207                 return EXYNOS4_##base;                          \
 208         } else if (cpu_is_exynos5()) {                          \
 209                 return EXYNOS5_##base;                          \
 210         }                                                       \
 211         return 0;                                               \
 212 }
 213
 214 SAMSUNG_BASE(adc, ADC_BASE)
 215 SAMSUNG_BASE(clock, CLOCK_BASE)
 216 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
 217 SAMSUNG_BASE(dp, DP_BASE)
 218 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 219 SAMSUNG_BASE(fimd, FIMD_BASE)
 220 SAMSUNG_BASE(i2c, I2C_BASE)
 221 SAMSUNG_BASE(i2s, I2S_BASE)
 222 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 223 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 224 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 225 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
 226 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
 227 SAMSUNG_BASE(pro_id, PRO_ID)
 228 SAMSUNG_BASE(mmc, MMC_BASE)
 229 SAMSUNG_BASE(modem, MODEM_BASE)
 230 SAMSUNG_BASE(sromc, SROMC_BASE)
 231 SAMSUNG_BASE(swreset, SWRESET)
 232 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 233 SAMSUNG_BASE(uart, UART_BASE)
 234 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
 235 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 236 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 237 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 238 SAMSUNG_BASE(power, POWER_BASE)
 239 SAMSUNG_BASE(spi, SPI_BASE)
 240 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 241 SAMSUNG_BASE(tzpc, TZPC_BASE)
 242 #endif
 243
 244 #endif  /* _EXYNOS4_CPU_H */