arch/arm/include/asm/arch-exynos/cpu.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  */
  21
  22 #ifndef _EXYNOS4_CPU_H
  23 #define _EXYNOS4_CPU_H
  24
  25 #define DEVICE_NOT_AVAILABLE            0
  26
  27 #define EXYNOS_CPU_NAME                 "Exynos"
  28 #define EXYNOS4_ADDR_BASE               0x10000000
  29
  30 /* EXYNOS4 */
  31 #define EXYNOS4_I2C_SPACING             0x10000
  32
  33 #define EXYNOS4_GPIO_PART3_BASE         0x03860000
  34 #define EXYNOS4_PRO_ID                  0x10000000
  35 #define EXYNOS4_SYSREG_BASE             0x10010000
  36 #define EXYNOS4_POWER_BASE              0x10020000
  37 #define EXYNOS4_SWRESET                 0x10020400
  38 #define EXYNOS4_CLOCK_BASE              0x10030000
  39 #define EXYNOS4_SYSTIMER_BASE           0x10050000
  40 #define EXYNOS4_WATCHDOG_BASE           0x10060000
  41 #define EXYNOS4_MIU_BASE                0x10600000
  42 #define EXYNOS4_DMC0_BASE               0x10400000
  43 #define EXYNOS4_DMC1_BASE               0x10410000
  44 #define EXYNOS4_GPIO_PART2_BASE         0x11000000
  45 #define EXYNOS4_GPIO_PART1_BASE         0x11400000
  46 #define EXYNOS4_FIMD_BASE               0x11C00000
  47 #define EXYNOS4_MIPI_DSIM_BASE          0x11C80000
  48 #define EXYNOS4_USBOTG_BASE             0x12480000
  49 #define EXYNOS4_MMC_BASE                0x12510000
  50 #define EXYNOS4_SROMC_BASE              0x12570000
  51 #define EXYNOS4_USB_HOST_EHCI_BASE      0x12580000
  52 #define EXYNOS4_USBPHY_BASE             0x125B0000
  53 #define EXYNOS4_UART_BASE               0x13800000
  54 #define EXYNOS4_I2C_BASE                0x13860000
  55 #define EXYNOS4_ADC_BASE                0x13910000
  56 #define EXYNOS4_SPI_BASE                0x13920000
  57 #define EXYNOS4_PWMTIMER_BASE           0x139D0000
  58 #define EXYNOS4_MODEM_BASE              0x13A00000
  59 #define EXYNOS4_USBPHY_CONTROL          0x10020704
  60 #define EXYNOS4_I2S_BASE                0xE2100000
  61
  62 #define EXYNOS4_GPIO_PART4_BASE         DEVICE_NOT_AVAILABLE
  63 #define EXYNOS4_DP_BASE                 DEVICE_NOT_AVAILABLE
  64 #define EXYNOS4_SPI_ISP_BASE            DEVICE_NOT_AVAILABLE
  65
  66 /* EXYNOS5 */
  67 #define EXYNOS5_I2C_SPACING             0x10000
  68
  69 #define EXYNOS5_GPIO_PART4_BASE         0x03860000
  70 #define EXYNOS5_PRO_ID                  0x10000000
  71 #define EXYNOS5_CLOCK_BASE              0x10010000
  72 #define EXYNOS5_POWER_BASE              0x10040000
  73 #define EXYNOS5_SWRESET                 0x10040400
  74 #define EXYNOS5_SYSREG_BASE             0x10050000
  75 #define EXYNOS5_WATCHDOG_BASE           0x101D0000
  76 #define EXYNOS5_DMC_PHY0_BASE           0x10C00000
  77 #define EXYNOS5_DMC_PHY1_BASE           0x10C10000
  78 #define EXYNOS5_GPIO_PART3_BASE         0x10D10000
  79 #define EXYNOS5_DMC_CTRL_BASE           0x10DD0000
  80 #define EXYNOS5_GPIO_PART1_BASE         0x11400000
  81 #define EXYNOS5_MIPI_DSIM_BASE          0x11D00000
  82 #define EXYNOS5_USB_HOST_EHCI_BASE      0x12110000
  83 #define EXYNOS5_USBPHY_BASE             0x12130000
  84 #define EXYNOS5_USBOTG_BASE             0x12140000
  85 #define EXYNOS5_MMC_BASE                0x12200000
  86 #define EXYNOS5_SROMC_BASE              0x12250000
  87 #define EXYNOS5_UART_BASE               0x12C00000
  88 #define EXYNOS5_I2C_BASE                0x12C60000
  89 #define EXYNOS5_SPI_BASE                0x12D20000
  90 #define EXYNOS5_I2S_BASE                0x12D60000
  91 #define EXYNOS5_PWMTIMER_BASE           0x12DD0000
  92 #define EXYNOS5_SPI_ISP_BASE            0x131A0000
  93 #define EXYNOS5_GPIO_PART2_BASE         0x13400000
  94 #define EXYNOS5_FIMD_BASE               0x14400000
  95 #define EXYNOS5_DP_BASE                 0x145B0000
  96
  97 #define EXYNOS5_ADC_BASE                DEVICE_NOT_AVAILABLE
  98 #define EXYNOS5_MODEM_BASE              DEVICE_NOT_AVAILABLE
  99
 100 #ifndef __ASSEMBLY__
 101 #include <asm/io.h>
 102 /* CPU detection macros */
 103 extern unsigned int s5p_cpu_id;
 104 extern unsigned int s5p_cpu_rev;
 105
 106 static inline int s5p_get_cpu_rev(void)
 107 {
 108         return s5p_cpu_rev;
 109 }
 110
 111 static inline void s5p_set_cpu_id(void)
 112 {
 113         unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
 114
 115         switch (pro_id) {
 116         case 0x200:
 117                 /* Exynos4210 EVT0 */
 118                 s5p_cpu_id = 0x4210;
 119                 s5p_cpu_rev = 0;
 120                 break;
 121         case 0x210:
 122                 /* Exynos4210 EVT1 */
 123                 s5p_cpu_id = 0x4210;
 124                 break;
 125         case 0x412:
 126                 /* Exynos4412 */
 127                 s5p_cpu_id = 0x4412;
 128                 break;
 129         case 0x520:
 130                 /* Exynos5250 */
 131                 s5p_cpu_id = 0x5250;
 132                 break;
 133         }
 134 }
 135
 136 static inline char *s5p_get_cpu_name(void)
 137 {
 138         return EXYNOS_CPU_NAME;
 139 }
 140
 141 #define IS_SAMSUNG_TYPE(type, id)                       \
 142 static inline int cpu_is_##type(void)                   \
 143 {                                                       \
 144         return (s5p_cpu_id >> 12) == id;                \
 145 }
 146
 147 IS_SAMSUNG_TYPE(exynos4, 0x4)
 148 IS_SAMSUNG_TYPE(exynos5, 0x5)
 149
 150 #define IS_EXYNOS_TYPE(type, id)                        \
 151 static inline int proid_is_##type(void)                 \
 152 {                                                       \
 153         return s5p_cpu_id == id;                        \
 154 }
 155
 156 IS_EXYNOS_TYPE(exynos4210, 0x4210)
 157 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 158
 159 #define SAMSUNG_BASE(device, base)                              \
 160 static inline unsigned int samsung_get_base_##device(void)      \
 161 {                                                               \
 162         if (cpu_is_exynos4())                                   \
 163                 return EXYNOS4_##base;                          \
 164         else if (cpu_is_exynos5())                              \
 165                 return EXYNOS5_##base;                          \
 166         else                                                    \
 167                 return 0;                                       \
 168 }
 169
 170 SAMSUNG_BASE(adc, ADC_BASE)
 171 SAMSUNG_BASE(clock, CLOCK_BASE)
 172 SAMSUNG_BASE(dp, DP_BASE)
 173 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 174 SAMSUNG_BASE(fimd, FIMD_BASE)
 175 SAMSUNG_BASE(i2c, I2C_BASE)
 176 SAMSUNG_BASE(i2s, I2S_BASE)
 177 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 178 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 179 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 180 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
 181 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
 182 SAMSUNG_BASE(pro_id, PRO_ID)
 183 SAMSUNG_BASE(mmc, MMC_BASE)
 184 SAMSUNG_BASE(modem, MODEM_BASE)
 185 SAMSUNG_BASE(sromc, SROMC_BASE)
 186 SAMSUNG_BASE(swreset, SWRESET)
 187 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 188 SAMSUNG_BASE(uart, UART_BASE)
 189 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
 190 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 191 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 192 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 193 SAMSUNG_BASE(power, POWER_BASE)
 194 SAMSUNG_BASE(spi, SPI_BASE)
 195 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 196 #endif
 197
 198 #endif  /* _EXYNOS4_CPU_H */