arch/arm/include/asm/arch-exynos/cpu.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _EXYNOS4_CPU_H
   9 #define _EXYNOS4_CPU_H
  10
  11 #define DEVICE_NOT_AVAILABLE            0
  12
  13 #define EXYNOS_CPU_NAME                 "Exynos"
  14 #define EXYNOS4_ADDR_BASE               0x10000000
  15
  16 /* EXYNOS4 Common*/
  17 #define EXYNOS4_I2C_SPACING             0x10000
  18
  19 #define EXYNOS4_GPIO_PART3_BASE         0x03860000
  20 #define EXYNOS4_PRO_ID                  0x10000000
  21 #define EXYNOS4_SYSREG_BASE             0x10010000
  22 #define EXYNOS4_POWER_BASE              0x10020000
  23 #define EXYNOS4_SWRESET                 0x10020400
  24 #define EXYNOS4_CLOCK_BASE              0x10030000
  25 #define EXYNOS4_SYSTIMER_BASE           0x10050000
  26 #define EXYNOS4_WATCHDOG_BASE           0x10060000
  27 #define EXYNOS4_TZPC_BASE               0x10110000
  28 #define EXYNOS4_DMC_CTRL_BASE           0x10400000
  29 #define EXYNOS4_MIU_BASE                0x10600000
  30 #define EXYNOS4_ACE_SFR_BASE            0x10830000
  31 #define EXYNOS4_GPIO_PART2_BASE         0x11000000
  32 #define EXYNOS4_GPIO_PART1_BASE         0x11400000
  33 #define EXYNOS4_FIMD_BASE               0x11C00000
  34 #define EXYNOS4_MIPI_DSIM_BASE          0x11C80000
  35 #define EXYNOS4_USBOTG_BASE             0x12480000
  36 #define EXYNOS4_MMC_BASE                0x12510000
  37 #define EXYNOS4_SROMC_BASE              0x12570000
  38 #define EXYNOS4_USB_HOST_EHCI_BASE      0x12580000
  39 #define EXYNOS4_USBPHY_BASE             0x125B0000
  40 #define EXYNOS4_UART_BASE               0x13800000
  41 #define EXYNOS4_I2C_BASE                0x13860000
  42 #define EXYNOS4_ADC_BASE                0x13910000
  43 #define EXYNOS4_SPI_BASE                0x13920000
  44 #define EXYNOS4_PWMTIMER_BASE           0x139D0000
  45 #define EXYNOS4_MODEM_BASE              0x13A00000
  46 #define EXYNOS4_USBPHY_CONTROL          0x10020704
  47 #define EXYNOS4_I2S_BASE                0xE2100000
  48
  49 #define EXYNOS4_GPIO_PART4_BASE         DEVICE_NOT_AVAILABLE
  50 #define EXYNOS4_DP_BASE                 DEVICE_NOT_AVAILABLE
  51 #define EXYNOS4_SPI_ISP_BASE            DEVICE_NOT_AVAILABLE
  52 #define EXYNOS4_DMC_PHY_BASE            DEVICE_NOT_AVAILABLE
  53 #define EXYNOS4_AUDIOSS_BASE            DEVICE_NOT_AVAILABLE
  54 #define EXYNOS4_USB_HOST_XHCI_BASE      DEVICE_NOT_AVAILABLE
  55 #define EXYNOS4_USB3PHY_BASE            DEVICE_NOT_AVAILABLE
  56 #define EXYNOS4_DMC_TZASC_BASE          DEVICE_NOT_AVAILABLE
  57
  58 /* EXYNOS4X12 */
  59 #define EXYNOS4X12_GPIO_PART3_BASE      0x03860000
  60 #define EXYNOS4X12_PRO_ID               0x10000000
  61 #define EXYNOS4X12_SYSREG_BASE          0x10010000
  62 #define EXYNOS4X12_POWER_BASE           0x10020000
  63 #define EXYNOS4X12_SWRESET              0x10020400
  64 #define EXYNOS4X12_USBPHY_CONTROL       0x10020704
  65 #define EXYNOS4X12_CLOCK_BASE           0x10030000
  66 #define EXYNOS4X12_SYSTIMER_BASE        0x10050000
  67 #define EXYNOS4X12_WATCHDOG_BASE        0x10060000
  68 #define EXYNOS4X12_TZPC_BASE            0x10110000
  69 #define EXYNOS4X12_DMC_CTRL_BASE        0x10600000
  70 #define EXYNOS4X12_GPIO_PART4_BASE      0x106E0000
  71 #define EXYNOS4X12_ACE_SFR_BASE         0x10830000
  72 #define EXYNOS4X12_GPIO_PART2_BASE      0x11000000
  73 #define EXYNOS4X12_GPIO_PART1_BASE      0x11400000
  74 #define EXYNOS4X12_FIMD_BASE            0x11C00000
  75 #define EXYNOS4X12_MIPI_DSIM_BASE       0x11C80000
  76 #define EXYNOS4X12_USBOTG_BASE          0x12480000
  77 #define EXYNOS4X12_MMC_BASE             0x12510000
  78 #define EXYNOS4X12_SROMC_BASE           0x12570000
  79 #define EXYNOS4X12_USB_HOST_EHCI_BASE   0x12580000
  80 #define EXYNOS4X12_USBPHY_BASE          0x125B0000
  81 #define EXYNOS4X12_UART_BASE            0x13800000
  82 #define EXYNOS4X12_I2C_BASE             0x13860000
  83 #define EXYNOS4X12_PWMTIMER_BASE        0x139D0000
  84
  85 #define EXYNOS4X12_ADC_BASE             DEVICE_NOT_AVAILABLE
  86 #define EXYNOS4X12_DP_BASE              DEVICE_NOT_AVAILABLE
  87 #define EXYNOS4X12_MODEM_BASE           DEVICE_NOT_AVAILABLE
  88 #define EXYNOS4X12_I2S_BASE             DEVICE_NOT_AVAILABLE
  89 #define EXYNOS4X12_SPI_BASE             DEVICE_NOT_AVAILABLE
  90 #define EXYNOS4X12_SPI_ISP_BASE         DEVICE_NOT_AVAILABLE
  91 #define EXYNOS4X12_DMC_PHY_BASE         DEVICE_NOT_AVAILABLE
  92 #define EXYNOS4X12_AUDIOSS_BASE         DEVICE_NOT_AVAILABLE
  93 #define EXYNOS4X12_USB_HOST_XHCI_BASE   DEVICE_NOT_AVAILABLE
  94 #define EXYNOS4X12_USB3PHY_BASE         DEVICE_NOT_AVAILABLE
  95 #define EXYNOS4X12_DMC_TZASC_BASE       DEVICE_NOT_AVAILABLE
  96
  97 /* EXYNOS5 */
  98 #define EXYNOS5_I2C_SPACING             0x10000
  99
 100 #define EXYNOS5_AUDIOSS_BASE            0x03810000
 101 #define EXYNOS5_GPIO_PART4_BASE         0x03860000
 102 #define EXYNOS5_PRO_ID                  0x10000000
 103 #define EXYNOS5_CLOCK_BASE              0x10010000
 104 #define EXYNOS5_POWER_BASE              0x10040000
 105 #define EXYNOS5_SWRESET                 0x10040400
 106 #define EXYNOS5_SYSREG_BASE             0x10050000
 107 #define EXYNOS5_TZPC_BASE               0x10100000
 108 #define EXYNOS5_WATCHDOG_BASE           0x101D0000
 109 #define EXYNOS5_ACE_SFR_BASE            0x10830000
 110 #define EXYNOS5_DMC_PHY_BASE            0x10C00000
 111 #define EXYNOS5_GPIO_PART3_BASE         0x10D10000
 112 #define EXYNOS5_DMC_CTRL_BASE           0x10DD0000
 113 #define EXYNOS5_GPIO_PART1_BASE         0x11400000
 114 #define EXYNOS5_MIPI_DSIM_BASE          0x11D00000
 115 #define EXYNOS5_USB_HOST_XHCI_BASE      0x12000000
 116 #define EXYNOS5_USB3PHY_BASE            0x12100000
 117 #define EXYNOS5_USB_HOST_EHCI_BASE      0x12110000
 118 #define EXYNOS5_USBPHY_BASE             0x12130000
 119 #define EXYNOS5_USBOTG_BASE             0x12140000
 120 #define EXYNOS5_MMC_BASE                0x12200000
 121 #define EXYNOS5_SROMC_BASE              0x12250000
 122 #define EXYNOS5_UART_BASE               0x12C00000
 123 #define EXYNOS5_I2C_BASE                0x12C60000
 124 #define EXYNOS5_SPI_BASE                0x12D20000
 125 #define EXYNOS5_I2S_BASE                0x12D60000
 126 #define EXYNOS5_PWMTIMER_BASE           0x12DD0000
 127 #define EXYNOS5_SPI_ISP_BASE            0x131A0000
 128 #define EXYNOS5_GPIO_PART2_BASE         0x13400000
 129 #define EXYNOS5_FIMD_BASE               0x14400000
 130 #define EXYNOS5_DP_BASE                 0x145B0000
 131
 132 #define EXYNOS5_ADC_BASE                DEVICE_NOT_AVAILABLE
 133 #define EXYNOS5_MODEM_BASE              DEVICE_NOT_AVAILABLE
 134 #define EXYNOS5_DMC_TZASC_BASE          DEVICE_NOT_AVAILABLE
 135
 136 /* EXYNOS5420 */
 137 #define EXYNOS5420_AUDIOSS_BASE         0x03810000
 138 #define EXYNOS5420_GPIO_PART5_BASE      0x03860000
 139 #define EXYNOS5420_PRO_ID               0x10000000
 140 #define EXYNOS5420_CLOCK_BASE           0x10010000
 141 #define EXYNOS5420_POWER_BASE           0x10040000
 142 #define EXYNOS5420_SWRESET              0x10040400
 143 #define EXYNOS5420_SYSREG_BASE          0x10050000
 144 #define EXYNOS5420_TZPC_BASE            0x100E0000
 145 #define EXYNOS5420_WATCHDOG_BASE        0x101D0000
 146 #define EXYNOS5420_ACE_SFR_BASE         0x10830000
 147 #define EXYNOS5420_DMC_PHY_BASE         0x10C00000
 148 #define EXYNOS5420_DMC_CTRL_BASE        0x10C20000
 149 #define EXYNOS5420_DMC_TZASC_BASE       0x10D40000
 150 #define EXYNOS5420_USB_HOST_EHCI_BASE   0x12110000
 151 #define EXYNOS5420_MMC_BASE             0x12200000
 152 #define EXYNOS5420_SROMC_BASE           0x12250000
 153 #define EXYNOS5420_UART_BASE            0x12C00000
 154 #define EXYNOS5420_I2C_BASE             0x12C60000
 155 #define EXYNOS5420_I2C_8910_BASE        0x12E00000
 156 #define EXYNOS5420_SPI_BASE             0x12D20000
 157 #define EXYNOS5420_I2S_BASE             0x12D60000
 158 #define EXYNOS5420_PWMTIMER_BASE        0x12DD0000
 159 #define EXYNOS5420_SPI_ISP_BASE         0x131A0000
 160 #define EXYNOS5420_GPIO_PART2_BASE      0x13400000
 161 #define EXYNOS5420_GPIO_PART3_BASE      0x13410000
 162 #define EXYNOS5420_GPIO_PART4_BASE      0x14000000
 163 #define EXYNOS5420_GPIO_PART1_BASE      0x14010000
 164 #define EXYNOS5420_MIPI_DSIM_BASE       0x14500000
 165 #define EXYNOS5420_DP_BASE              0x145B0000
 166
 167 #define EXYNOS5420_USBPHY_BASE          DEVICE_NOT_AVAILABLE
 168 #define EXYNOS5420_USBOTG_BASE          DEVICE_NOT_AVAILABLE
 169 #define EXYNOS5420_FIMD_BASE            DEVICE_NOT_AVAILABLE
 170 #define EXYNOS5420_ADC_BASE             DEVICE_NOT_AVAILABLE
 171 #define EXYNOS5420_MODEM_BASE           DEVICE_NOT_AVAILABLE
 172 #define EXYNOS5420_USB3PHY_BASE         DEVICE_NOT_AVAILABLE
 173 #define EXYNOS5420_USB_HOST_XHCI_BASE   DEVICE_NOT_AVAILABLE
 174
 175 #ifndef __ASSEMBLY__
 176 #include <asm/io.h>
 177 /* CPU detection macros */
 178 extern unsigned int s5p_cpu_id;
 179 extern unsigned int s5p_cpu_rev;
 180
 181 static inline int s5p_get_cpu_rev(void)
 182 {
 183         return s5p_cpu_rev;
 184 }
 185
 186 static inline void s5p_set_cpu_id(void)
 187 {
 188         unsigned int pro_id = readl(EXYNOS4_PRO_ID);
 189         unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
 190         unsigned int cpu_rev = pro_id & 0x000000FF;
 191
 192         switch (cpu_id) {
 193         case 0x200:
 194                 /* Exynos4210 EVT0 */
 195                 s5p_cpu_id = 0x4210;
 196                 s5p_cpu_rev = 0;
 197                 break;
 198         case 0x210:
 199                 /* Exynos4210 EVT1 */
 200                 s5p_cpu_id = 0x4210;
 201                 s5p_cpu_rev = cpu_rev;
 202                 break;
 203         case 0x412:
 204                 /* Exynos4412 */
 205                 s5p_cpu_id = 0x4412;
 206                 s5p_cpu_rev = cpu_rev;
 207                 break;
 208         case 0x520:
 209                 /* Exynos5250 */
 210                 s5p_cpu_id = 0x5250;
 211                 break;
 212         case 0x420:
 213                 /* Exynos5420 */
 214                 s5p_cpu_id = 0x5420;
 215                 break;
 216         }
 217 }
 218
 219 static inline char *s5p_get_cpu_name(void)
 220 {
 221         return EXYNOS_CPU_NAME;
 222 }
 223
 224 #define IS_SAMSUNG_TYPE(type, id)                       \
 225 static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
 226 {                                                       \
 227         return (s5p_cpu_id >> 12) == id;                \
 228 }
 229
 230 IS_SAMSUNG_TYPE(exynos4, 0x4)
 231 IS_SAMSUNG_TYPE(exynos5, 0x5)
 232
 233 #define IS_EXYNOS_TYPE(type, id)                        \
 234 static inline int __attribute__((no_instrument_function)) \
 235         proid_is_##type(void)                           \
 236 {                                                       \
 237         return s5p_cpu_id == id;                        \
 238 }
 239
 240 IS_EXYNOS_TYPE(exynos4210, 0x4210)
 241 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 242 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 243 IS_EXYNOS_TYPE(exynos5420, 0x5420)
 244
 245 #define SAMSUNG_BASE(device, base)                              \
 246 static inline unsigned int __attribute__((no_instrument_function)) \
 247         samsung_get_base_##device(void) \
 248 {                                                               \
 249         if (cpu_is_exynos4()) {                         \
 250                 if (proid_is_exynos4412())                      \
 251                         return EXYNOS4X12_##base;               \
 252                 return EXYNOS4_##base;                          \
 253         } else if (cpu_is_exynos5()) {                          \
 254                 if (proid_is_exynos5420())                      \
 255                         return EXYNOS5420_##base;               \
 256                 return EXYNOS5_##base;                          \
 257         }                                                       \
 258         return 0;                                               \
 259 }
 260
 261 SAMSUNG_BASE(adc, ADC_BASE)
 262 SAMSUNG_BASE(clock, CLOCK_BASE)
 263 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
 264 SAMSUNG_BASE(dp, DP_BASE)
 265 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 266 SAMSUNG_BASE(fimd, FIMD_BASE)
 267 SAMSUNG_BASE(i2c, I2C_BASE)
 268 SAMSUNG_BASE(i2s, I2S_BASE)
 269 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 270 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 271 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 272 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
 273 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
 274 SAMSUNG_BASE(pro_id, PRO_ID)
 275 SAMSUNG_BASE(mmc, MMC_BASE)
 276 SAMSUNG_BASE(modem, MODEM_BASE)
 277 SAMSUNG_BASE(sromc, SROMC_BASE)
 278 SAMSUNG_BASE(swreset, SWRESET)
 279 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 280 SAMSUNG_BASE(uart, UART_BASE)
 281 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
 282 SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
 283 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 284 SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
 285 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 286 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 287 SAMSUNG_BASE(power, POWER_BASE)
 288 SAMSUNG_BASE(spi, SPI_BASE)
 289 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 290 SAMSUNG_BASE(tzpc, TZPC_BASE)
 291 SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
 292 SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
 293 SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
 294 SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
 295 #endif
 296
 297 #endif  /* _EXYNOS4_CPU_H */