arch/arm/include/asm/arch-exynos/dp_info.h

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: Donghwa Lee <dh09.lee@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef _DP_INFO_H
  23 #define _DP_INFO_H
  24
  25 #define msleep(a)                       udelay(a * 1000)
  26
  27 #define DP_TIMEOUT_LOOP_COUNT           100
  28 #define MAX_CR_LOOP                     5
  29 #define MAX_EQ_LOOP                     4
  30
  31 #define EXYNOS_DP_SUCCESS               0
  32
  33 enum {
  34         DP_DISABLE,
  35         DP_ENABLE,
  36 };
  37
  38 struct edp_disp_info {
  39         char *name;
  40         unsigned int h_total;
  41         unsigned int h_res;
  42         unsigned int h_sync_width;
  43         unsigned int h_back_porch;
  44         unsigned int h_front_porch;
  45         unsigned int v_total;
  46         unsigned int v_res;
  47         unsigned int v_sync_width;
  48         unsigned int v_back_porch;
  49         unsigned int v_front_porch;
  50
  51         unsigned int v_sync_rate;
  52 };
  53
  54 struct edp_link_train_info {
  55         unsigned int lt_status;
  56
  57         unsigned int ep_loop;
  58         unsigned int cr_loop[4];
  59
  60 };
  61
  62 struct edp_video_info {
  63         unsigned int master_mode;
  64         unsigned int bist_mode;
  65         unsigned int bist_pattern;
  66
  67         unsigned int h_sync_polarity;
  68         unsigned int v_sync_polarity;
  69         unsigned int interlaced;
  70
  71         unsigned int color_space;
  72         unsigned int dynamic_range;
  73         unsigned int ycbcr_coeff;
  74         unsigned int color_depth;
  75 };
  76
  77 struct edp_device_info {
  78         struct edp_disp_info disp_info;
  79         struct edp_link_train_info lt_info;
  80         struct edp_video_info video_info;
  81
  82         /*below info get from panel during training*/
  83         unsigned char lane_bw;
  84         unsigned char lane_cnt;
  85         unsigned char dpcd_rev;
  86         /*support enhanced frame cap */
  87         unsigned char dpcd_efc;
  88 };
  89
  90 enum analog_power_block {
  91         AUX_BLOCK,
  92         CH0_BLOCK,
  93         CH1_BLOCK,
  94         CH2_BLOCK,
  95         CH3_BLOCK,
  96         ANALOG_TOTAL,
  97         POWER_ALL
  98 };
  99
 100 enum pll_status {
 101         PLL_UNLOCKED = 0,
 102         PLL_LOCKED
 103 };
 104
 105 enum {
 106         COLOR_RGB,
 107         COLOR_YCBCR422,
 108         COLOR_YCBCR444
 109 };
 110
 111 enum {
 112         VESA,
 113         CEA
 114 };
 115
 116 enum {
 117         COLOR_YCBCR601,
 118         COLOR_YCBCR709
 119 };
 120
 121 enum {
 122         COLOR_6,
 123         COLOR_8,
 124         COLOR_10,
 125         COLOR_12
 126 };
 127
 128 enum {
 129         DP_LANE_BW_1_62 = 0x06,
 130         DP_LANE_BW_2_70 = 0x0a,
 131 };
 132
 133 enum {
 134         DP_LANE_CNT_1 = 1,
 135         DP_LANE_CNT_2 = 2,
 136         DP_LANE_CNT_4 = 4,
 137 };
 138
 139 enum {
 140         DP_DPCD_REV_10 = 0x10,
 141         DP_DPCD_REV_11 = 0x11,
 142 };
 143
 144 enum {
 145         DP_LT_NONE,
 146         DP_LT_START,
 147         DP_LT_CR,
 148         DP_LT_ET,
 149         DP_LT_FINISHED,
 150         DP_LT_FAIL,
 151 };
 152
 153 enum  {
 154         PRE_EMPHASIS_LEVEL_0,
 155         PRE_EMPHASIS_LEVEL_1,
 156         PRE_EMPHASIS_LEVEL_2,
 157         PRE_EMPHASIS_LEVEL_3,
 158 };
 159
 160 enum {
 161         PRBS7,
 162         D10_2,
 163         TRAINING_PTN1,
 164         TRAINING_PTN2,
 165         DP_NONE
 166 };
 167
 168 enum {
 169         VOLTAGE_LEVEL_0,
 170         VOLTAGE_LEVEL_1,
 171         VOLTAGE_LEVEL_2,
 172         VOLTAGE_LEVEL_3,
 173 };
 174
 175 enum pattern_type {
 176         NO_PATTERN,
 177         COLOR_RAMP,
 178         BALCK_WHITE_V_LINES,
 179         COLOR_SQUARE,
 180         INVALID_PATTERN,
 181         COLORBAR_32,
 182         COLORBAR_64,
 183         WHITE_GRAY_BALCKBAR_32,
 184         WHITE_GRAY_BALCKBAR_64,
 185         MOBILE_WHITEBAR_32,
 186         MOBILE_WHITEBAR_64
 187 };
 188
 189 enum {
 190         CALCULATED_M,
 191         REGISTER_M
 192 };
 193
 194 enum {
 195         VIDEO_TIMING_FROM_CAPTURE,
 196         VIDEO_TIMING_FROM_REGISTER
 197 };
 198
 199
 200 struct exynos_dp_platform_data {
 201         struct edp_device_info *edp_dev_info;
 202 };
 203
 204 #ifdef CONFIG_EXYNOS_DP
 205 unsigned int exynos_init_dp(void);
 206 #else
 207 unsigned int exynos_init_dp(void)
 208 {
 209         return 0;
 210 }
 211 #endif
 212
 213 void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
 214
 215 #endif /* _DP_INFO_H */