2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
15 * The vast majority of this file is taken from the Linux kernel at
19 #ifndef __IOMUX_MX51_H__
20 #define __IOMUX_MX51_H__
22 #include <asm/imx-common/iomux-v3.h>
24 /* Pad control groupings */
25 #define MX51_UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
26 PAD_CTL_HYS | PAD_CTL_SRE_FAST)
27 #define MX51_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
28 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
30 #define MX51_ESDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
31 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
33 #define MX51_USBH_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
34 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
35 #define MX51_ECSPI_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS | \
36 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
37 #define MX51_SDHCI_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
38 PAD_CTL_SRE_FAST | PAD_CTL_DVS)
39 #define MX51_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
41 #define MX51_PAD_CTRL_2 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS)
42 #define MX51_PAD_CTRL_4 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
43 #define MX51_PAD_CTRL_5 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
45 #define MX51_PAD_CTRL_2 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS)
46 #define MX51_PAD_CTRL_3 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
47 #define MX51_PAD_CTRL_4 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
48 #define MX51_PAD_CTRL_5 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
51 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
52 * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
56 /* PAD MUX ALT INPSE PATH PADCTRL */
58 MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
59 MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
60 MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
61 MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
62 MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
63 MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
64 MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
65 MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
66 MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
67 MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
68 MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
69 MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
70 MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
71 MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
72 MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
73 MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
74 MX51_PAD_EIM_A21__BOOT_UART_SRC1 = IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL),
75 MX51_PAD_EIM_A21__EIM_A21 = IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL),
76 MX51_PAD_EIM_A21__GPIO2_15 = IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
77 MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
78 MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
79 MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
80 MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
81 MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
82 MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
83 MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
84 MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
85 MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
86 MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
87 MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
88 MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
89 MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
90 MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
91 MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
92 MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
93 MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
94 MX51_PAD_EIM_CS5__CSI1_D7 = IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL),
95 MX51_PAD_EIM_CS5__DISP1_EXT_CLK = IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL),
96 MX51_PAD_EIM_CS5__EIM_CS5 = IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL),
97 MX51_PAD_EIM_CS5__GPIO2_30 = IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
98 MX51_PAD_EIM_CS5__USBOTG_DIR = IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL),
99 MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
100 MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
101 MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
102 MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
103 MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0 = IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
104 MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1 = IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
105 MX51_PAD_DRAM_SDCLK__DRAM_SDCLK = IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
106 MX51_PAD_DRAM_SDQS0__DRAM_SDQS0 = IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
107 MX51_PAD_DRAM_SDQS1__DRAM_SDQS1 = IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
108 MX51_PAD_DRAM_SDQS2__DRAM_SDQS2 = IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
109 MX51_PAD_DRAM_SDQS3__DRAM_SDQS3 = IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
110 MX51_PAD_DRAM_CS0__DRAM_CS0 = IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
111 MX51_PAD_DRAM_CS1__DRAM_CS1 = IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
112 MX51_PAD_DRAM_DQM0__DRAM_DQM0 = IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
113 MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
114 MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
115 MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
116 MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
117 MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
118 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
119 MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
120 MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
121 MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
122 MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
123 MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
124 MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
125 MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
126 MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
127 MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
128 MX51_PAD_NANDF_CS2__NANDF_CS2 = IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
129 MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
130 MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
131 MX51_PAD_NANDF_CS2__GPIO3_18 = IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
132 MX51_PAD_NANDF_CS2__SD4_CLK = IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
133 MX51_PAD_NANDF_CS2__CSPI_SCLK = IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL),
134 MX51_PAD_NANDF_CS2__USBH3_H1_DP = IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
135 MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
136 MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
137 MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
138 MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
139 MX51_PAD_NANDF_CS5__FEC_TDATA2 = IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
140 MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
141 MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
142 MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
143 MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
144 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
145 MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
146 MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
147 MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
148 MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
149 MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
150 MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
151 MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
152 MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
153 MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
154 MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
155 MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
156 MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
157 MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
158 MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
159 MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
160 MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
161 MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
162 MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
163 MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
164 MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
165 MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
166 MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
167 MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
168 MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
169 MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
170 MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
171 MX51_PAD_CSI2_VSYNC__CSI2_VSYNC = IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL),
172 MX51_PAD_CSI2_VSYNC__GPIO4_13 = IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
173 MX51_PAD_CSI2_HSYNC__CSI2_HSYNC = IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL),
174 MX51_PAD_CSI2_HSYNC__GPIO4_14 = IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
175 MX51_PAD_I2C1_CLK__GPIO4_16 = IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
176 MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
177 MX51_PAD_I2C1_DAT__GPIO4_17 = IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
178 MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
179 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
180 MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
181 MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
182 MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
183 MX51_PAD_CSPI1_SS1__ECSPI1_SS1 = IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
184 MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
185 MX51_PAD_CSPI1_RDY__ECSPI1_RDY = IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
186 MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
187 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
188 MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
189 MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
190 MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
191 MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
192 MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
193 MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
194 MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
195 MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
196 MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
197 MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
198 MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
199 MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
200 MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
201 MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
202 MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
203 MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
204 MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
205 MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
206 MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
207 MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
208 MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
209 MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
210 MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
211 MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
212 MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS = IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL),
213 MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 = IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL),
214 MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 = IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL),
215 MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL),
216 MX51_PAD_DISP1_DAT0__DISP1_DAT0 = IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL),
217 MX51_PAD_DISP1_DAT1__DISP1_DAT1 = IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL),
218 MX51_PAD_DISP1_DAT2__DISP1_DAT2 = IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL),
219 MX51_PAD_DISP1_DAT3__DISP1_DAT3 = IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL),
220 MX51_PAD_DISP1_DAT4__DISP1_DAT4 = IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL),
221 MX51_PAD_DISP1_DAT5__DISP1_DAT5 = IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL),
222 MX51_PAD_DISP1_DAT6__BOOT_USB_SRC = IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL),
223 MX51_PAD_DISP1_DAT6__DISP1_DAT6 = IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL),
224 MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG = IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL),
225 MX51_PAD_DISP1_DAT7__DISP1_DAT7 = IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL),
226 MX51_PAD_DISP1_DAT8__BOOT_SRC0 = IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL),
227 MX51_PAD_DISP1_DAT8__DISP1_DAT8 = IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL),
228 MX51_PAD_DISP1_DAT9__BOOT_SRC1 = IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL),
229 MX51_PAD_DISP1_DAT9__DISP1_DAT9 = IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL),
230 MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE = IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL),
231 MX51_PAD_DISP1_DAT10__DISP1_DAT10 = IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL),
232 MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 = IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL),
233 MX51_PAD_DISP1_DAT11__DISP1_DAT11 = IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL),
234 MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL = IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL),
235 MX51_PAD_DISP1_DAT12__DISP1_DAT12 = IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL),
236 MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 = IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
237 MX51_PAD_DISP1_DAT13__DISP1_DAT13 = IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL),
238 MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 = IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
239 MX51_PAD_DISP1_DAT14__DISP1_DAT14 = IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL),
240 MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH = IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
241 MX51_PAD_DISP1_DAT15__DISP1_DAT15 = IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL),
242 MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 = IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL),
243 MX51_PAD_DISP1_DAT16__DISP1_DAT16 = IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL),
244 MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 = IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
245 MX51_PAD_DISP1_DAT17__DISP1_DAT17 = IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL),
246 MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 = IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
247 MX51_PAD_DISP1_DAT18__DISP1_DAT18 = IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
248 MX51_PAD_DISP1_DAT18__DISP2_PIN11 = IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
249 MX51_PAD_DISP1_DAT18__DISP2_PIN5 = IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
250 MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 = IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
251 MX51_PAD_DISP1_DAT19__DISP1_DAT19 = IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL),
252 MX51_PAD_DISP1_DAT19__DISP2_PIN12 = IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
253 MX51_PAD_DISP1_DAT19__DISP2_PIN6 = IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
254 MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 = IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL),
255 MX51_PAD_DISP1_DAT20__DISP1_DAT20 = IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL),
256 MX51_PAD_DISP1_DAT20__DISP2_PIN13 = IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL),
257 MX51_PAD_DISP1_DAT20__DISP2_PIN7 = IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL),
258 MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 = IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL),
259 MX51_PAD_DISP1_DAT21__DISP1_DAT21 = IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL),
260 MX51_PAD_DISP1_DAT21__DISP2_PIN14 = IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
261 MX51_PAD_DISP1_DAT21__DISP2_PIN8 = IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
262 MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 = IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL),
263 MX51_PAD_DISP1_DAT22__DISP1_DAT22 = IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL),
264 MX51_PAD_DISP1_DAT22__DISP2_D0_CS = IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
265 MX51_PAD_DISP1_DAT22__DISP2_DAT16 = IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
266 MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 = IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL),
267 MX51_PAD_DISP1_DAT23__DISP1_DAT23 = IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL),
268 MX51_PAD_DISP1_DAT23__DISP2_D1_CS = IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
269 MX51_PAD_DISP1_DAT23__DISP2_DAT17 = IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
270 MX51_PAD_DISP1_DAT23__DISP2_SER_CS = IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
271 MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
272 MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
273 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
274 MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
275 MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
276 MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
277 MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
278 MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
279 MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
280 MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
281 MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
282 MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
283 MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
284 MX51_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL),
285 MX51_PAD_GPIO1_1__CSPI_MISO = IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL),
286 MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
287 MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
288 MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
289 MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
290 MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
291 MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
292 MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
293 MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
294 MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
295 MX51_PAD_GPIO1_4__DISP2_EXT_CLK = IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL),
296 MX51_PAD_GPIO1_4__EIM_RDY = IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL),
297 MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL),
298 MX51_PAD_GPIO1_4__WDOG1_WDOG_B = IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL),
299 MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
300 MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
301 MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
302 MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
303 MX51_PAD_GPIO1_8__CSI2_DATA_EN = IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL),
304 MX51_PAD_GPIO1_8__GPIO1_8 = IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL),
305 MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
306 MX51_PAD_GPIO1_9__CCM_OUT_1 = IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL),
307 MX51_PAD_GPIO1_9__DISP2_D1_CS = IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL),
308 MX51_PAD_GPIO1_9__DISP2_SER_CS = IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL),
309 MX51_PAD_GPIO1_9__GPIO1_9 = IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL),
310 MX51_PAD_GPIO1_9__SD2_LCTL = IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL),
311 MX51_PAD_GPIO1_9__USBH3_OC = IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL),
312 MX51_PAD_GPIO1_8__USBH3_PWR = IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL),
313 MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
314 MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
315 MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
316 MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
317 MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
318 MX51_GRP_DDRAPUS = IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
319 MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
320 MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
321 MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
322 MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
323 MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
324 MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
325 MX51_GRP_DRAM_SR_B1 = IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
326 MX51_GRP_DDRPUS = IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
327 MX51_GRP_DRAM_SR_B2 = IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
328 MX51_GRP_PKEADDR = IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
329 MX51_GRP_DRAM_SR_B4 = IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
330 MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
331 MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
332 MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
333 MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
334 MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
337 #endif /* __IOMUX_MX51_H__ */
projects / karo-tx-uboot.git / blob