3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_ARCH_CLOCK_H
9 #define __ASM_ARCH_CLOCK_H
13 #ifdef CONFIG_SYS_MX6_HCLK
14 #define MXC_HCLK CONFIG_SYS_MX6_HCLK
16 #define MXC_HCLK 24000000
19 #ifdef CONFIG_SYS_MX6_CLK32
20 #define MXC_CLK32 CONFIG_SYS_MX6_CLK32
22 #define MXC_CLK32 32768
43 #ifdef CONFIG_VIDEO_MXS
58 /* Source clock this clk depends on */
60 /* Secondary clock to enable/disable with this clock */
61 struct clk *secondary;
62 /* Current clock rate */
64 /* Reference count of clock enable/disable */
66 /* Register bit position for clock's enable/disable control. */
68 /* Register address for clock's enable/disable control. */
72 * Function ptr to recalculate the clock's rate based on parent
75 void (*recalc) (struct clk *);
77 * Function ptr to set the clock to a new rate. The rate must match a
78 * supported rate returned from round_rate. Leave blank if clock is not
81 int (*set_rate) (struct clk *, unsigned long);
83 * Function ptr to round the requested clock rate to the nearest
84 * supported rate that is less than or equal to the requested rate.
86 unsigned long (*round_rate) (struct clk *, unsigned long);
88 * Function ptr to enable the clock. Leave blank if clock can not
91 int (*enable) (struct clk *);
93 * Function ptr to disable the clock. Leave blank if clock can not
96 void (*disable) (struct clk *);
97 /* Function ptr to set the parent clock of the clock. */
98 int (*set_parent) (struct clk *, struct clk *);
101 u32 imx_get_uartclk(void);
102 u32 imx_get_fecclk(void);
103 unsigned int mxc_get_clock(enum mxc_clock clk);
104 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
105 void setup_gpmi_io_clk(u32 cfg);
106 void hab_caam_clock_enable(unsigned char enable);
107 void enable_ocotp_clk(unsigned char enable);
108 void enable_usboh3_clk(unsigned char enable);
109 void enable_uart_clk(unsigned char enable);
110 int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
111 int enable_sata_clock(void);
112 void disable_sata_clock(void);
113 int enable_pcie_clock(void);
114 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
115 int enable_spi_clk(unsigned char enable, unsigned spi_num);
116 void enable_ipu_clock(void);
117 int enable_fec_anatop_clock(enum enet_freq freq);
118 void enable_enet_clk(unsigned char enable);
119 void enable_qspi_clk(int qspi_num);
120 void enable_thermal_clk(void);
121 void ipu_clk_enable(void);
122 void ipu_clk_disable(void);
123 void ipu_di_clk_enable(int di);
124 void ipu_di_clk_disable(int di);
125 void ldb_clk_enable(int ldb);
126 void ldb_clk_disable(int ldb);
127 #ifdef CONFIG_VIDEO_MXS
128 void lcdif_clk_enable(void);
129 void lcdif_clk_disable(void);
131 #endif /* __ASM_ARCH_CLOCK_H */