2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
65 /* CCR_WB does not exist on i.MX6SX/UL */
66 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
67 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
68 #define MXC_CCM_CCR_COSC_EN (1 << 12)
69 #ifdef CONFIG_SOC_MX6SX
70 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
72 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
74 #define MXC_CCM_CCR_OSCNT_OFFSET 0
76 /* Define the bits in register CCDR */
77 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
78 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
79 /* Exists on i.MX6QP */
80 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
82 /* Define the bits in register CSR */
83 #define MXC_CCM_CSR_COSC_READY (1 << 5)
84 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
86 /* Define the bits in register CCSR */
87 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
88 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
89 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
90 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
91 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
92 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
93 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
94 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
95 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
96 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
97 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
99 /* Define the bits in register CACRR */
100 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
101 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
103 /* Define the bits in register CBCDR */
104 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
105 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
106 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
107 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
108 /* MMDC_CH0 not exists on i.MX6SX */
109 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
110 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
111 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
113 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
115 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
116 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
117 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
118 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
119 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
120 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
121 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
122 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
124 /* Define the bits in register CBCMR */
125 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
126 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
127 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
128 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
129 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
130 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
131 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
132 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
133 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
134 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
135 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
136 #ifndef CONFIG_SOC_MX6SX
137 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
138 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
139 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
140 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
142 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
143 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
144 #ifndef CONFIG_SOC_MX6SX
145 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
147 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
148 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
149 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
150 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
151 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
152 /* Exists on i.MX6QP */
153 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
155 /* Define the bits in register CSCMR1 */
156 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
157 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
158 /* QSPI1 exist on i.MX6SX/UL */
159 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
160 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
161 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
162 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
163 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
164 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
165 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
166 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
167 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
168 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
169 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
170 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
171 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
172 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
173 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
174 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
175 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
176 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
177 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
178 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
179 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
180 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
181 /* QSPI1 exist on i.MX6SX/UL */
182 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
183 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
184 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
185 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
186 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
188 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
190 /* Define the bits in register CSCMR2 */
191 #ifdef CONFIG_SOC_MX6SX
192 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
193 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
195 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
196 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
197 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
198 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
199 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
200 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
201 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
203 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
204 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
206 /* Define the bits in register CSCDR1 */
207 #ifndef CONFIG_SOC_MX6SX
208 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
209 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
211 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
212 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)
213 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
214 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET)
215 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
217 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
218 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
219 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
220 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
221 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
222 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
223 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
224 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
225 #ifndef CONFIG_SOC_MX6SX
226 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
227 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
228 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
229 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
231 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
232 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
233 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
234 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
236 /* Define the bits in register CS1CDR */
237 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
238 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
239 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
240 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
241 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
242 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
243 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
244 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
245 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
246 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
247 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
248 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
250 /* Define the bits in register CS2CDR */
251 /* QSPI2 on i.MX6SX */
252 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
253 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
254 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
255 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
256 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
257 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
258 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
259 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
260 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
262 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
263 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
264 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
265 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
266 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
267 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
269 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
270 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
271 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
272 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
273 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
274 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
276 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
277 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
278 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
279 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
280 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
281 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
282 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
283 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
284 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
285 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
286 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
287 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
289 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
290 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
291 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
292 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
293 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
294 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
295 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
296 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
298 /* Define the bits in register CDCDR */
299 #ifndef CONFIG_SOC_MX6SX
300 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
301 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
302 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
303 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
305 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
306 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
307 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
308 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
309 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
310 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
311 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
312 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
313 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
314 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
315 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
316 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
318 /* Define the bits in register CHSCCDR */
319 #ifdef CONFIG_SOC_MX6SX
320 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
321 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
322 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
323 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
324 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
325 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
326 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
327 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
328 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
329 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
330 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
331 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
333 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
334 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
335 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
336 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
337 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
338 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
339 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
340 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
341 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
342 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
343 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
344 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
347 #define CHSCCDR_CLK_SEL_LDB_DI0 3
348 #define CHSCCDR_PODF_DIVIDE_BY_3 2
349 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
351 /* Define the bits in register CSCDR2 */
352 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
353 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
354 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
355 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
357 /* All IPU2_DI1 are LCDIF1 on MX6SX */
358 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
359 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
360 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
361 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
362 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
363 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
364 /* All IPU2_DI0 are LCDIF2 on MX6SX */
365 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
366 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
367 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
368 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
369 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
370 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
372 /* Define the bits in register CSCDR3 */
373 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
374 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
375 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
376 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
377 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
378 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
379 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
380 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
382 /* Define the bits in register CDHIPR */
383 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
384 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
385 #ifndef CONFIG_SOC_MX6SX
386 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
388 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
389 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
390 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
391 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
393 /* Define the bits in register CLPCR */
394 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
395 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
396 #ifndef CONFIG_SOC_MX6SX
397 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
398 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
399 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
401 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
402 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
403 #ifndef CONFIG_SOC_MX6SX
404 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
405 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
407 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
408 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
409 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
410 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
411 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
412 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
413 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
414 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
415 #ifndef CONFIG_SOC_MX6SX
416 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
417 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
418 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
420 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
421 #define MXC_CCM_CLPCR_LPM_OFFSET 0
423 /* Define the bits in register CISR */
424 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
425 #ifndef CONFIG_SOC_MX6SX
426 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
428 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
429 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
430 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
431 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
432 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
433 #define MXC_CCM_CISR_COSC_READY (1 << 6)
434 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
436 /* Define the bits in register CIMR */
437 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
438 #ifndef CONFIG_SOC_MX6SX
439 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
441 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
442 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
443 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
444 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
445 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
446 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
447 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
449 /* Define the bits in register CCOSR */
450 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
451 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
452 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
453 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
454 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
455 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
456 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
457 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
458 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
459 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
460 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
462 /* Define the bits in registers CGPR */
463 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
464 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
465 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
466 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
468 /* Define the bits in registers CCGRx */
469 #define MXC_CCM_CCGR_CG_MASK 3
471 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
472 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
473 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
474 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
475 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
476 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
477 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
478 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
479 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
480 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
481 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
482 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
483 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
484 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
485 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
486 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
487 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
488 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
489 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
490 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
491 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
492 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
493 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
494 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
495 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
496 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
497 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
498 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
499 #ifdef CONFIG_SOC_MX6SX
500 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
501 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
503 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
504 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
507 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
508 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
509 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
510 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
511 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
512 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
513 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
514 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
515 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
516 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
517 /* CCGR1_ENET does not exist on i.MX6SX/UL */
518 #define MXC_CCM_CCGR1_ENET_OFFSET 10
519 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
520 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
521 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
522 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
523 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
524 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
525 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
526 #ifdef CONFIG_SOC_MX6SX
527 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
528 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
530 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
531 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
532 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
533 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
534 #ifndef CONFIG_SOC_MX6SX
535 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
536 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
538 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
539 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
540 #ifdef CONFIG_SOC_MX6SX
541 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
542 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
543 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
544 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
547 #ifndef CONFIG_SOC_MX6SX
548 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
549 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
551 #define MXC_CCM_CCGR2_CSI_OFFSET 2
552 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
554 #ifndef CONFIG_SOC_MX6SX
555 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
556 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
558 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
559 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
560 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
561 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
562 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
563 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
564 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
565 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
566 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
567 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
568 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
569 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
570 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
571 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
572 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
573 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
574 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
575 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
576 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
577 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
578 #ifdef CONFIG_SOC_MX6SX
579 #define MXC_CCM_CCGR2_LCD_OFFSET 28
580 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
581 #define MXC_CCM_CCGR2_PXP_OFFSET 30
582 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
584 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
585 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
586 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
587 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
590 /* Exist on i.MX6SX */
591 #define MXC_CCM_CCGR3_M4_OFFSET 2
592 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
593 #define MXC_CCM_CCGR3_ENET_OFFSET 4
594 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
595 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
596 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
598 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
599 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
600 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
601 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
602 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
603 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
605 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
606 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
607 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
608 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
609 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
610 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
611 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
612 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
614 /* QSPI1 exists on i.MX6SX/UL */
615 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
616 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
618 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
619 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
620 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
621 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
623 /* A7_CLKDIV/WDOG1 on i.MX6UL */
624 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
625 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
626 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
627 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
629 #define MXC_CCM_CCGR3_MLB_OFFSET 18
630 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
631 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
632 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
633 #ifndef CONFIG_SOC_MX6SX
634 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
635 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
637 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
638 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
639 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
640 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
642 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
643 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
644 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
645 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
647 /* GPIO4 on i.MX6UL */
648 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
649 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
652 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
653 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
656 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
657 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
658 /* QSPI2 on i.MX6SX */
659 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
660 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
661 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
662 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
663 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
664 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
665 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
666 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
667 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
668 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
669 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
670 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
671 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
672 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
673 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
674 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
675 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
676 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
677 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
678 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
679 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
680 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
681 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
682 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
684 #define MXC_CCM_CCGR5_ROM_OFFSET 0
685 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
686 #ifndef CONFIG_SOC_MX6SX
687 #define MXC_CCM_CCGR5_SATA_OFFSET 4
688 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
690 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
691 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
692 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
693 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
694 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
695 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
696 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
697 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
698 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
699 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
700 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
701 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
702 #define MXC_CCM_CCGR5_UART_OFFSET 24
703 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
704 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
705 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
706 #ifdef CONFIG_SOC_MX6SX
707 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
708 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
709 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
710 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
713 /* PRG_CLK0 exists on i.MX6QP */
714 #define MXC_CCM_CCGR6_PRG_CLK0_OFFSET 24
715 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
717 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
718 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
719 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
720 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
721 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
722 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
723 /* GPMI/BCH on i.MX6UL */
724 #define MXC_CCM_CCGR6_BCH_OFFSET 6
725 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
726 #define MXC_CCM_CCGR6_GPMI_OFFSET 8
727 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
729 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
730 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
731 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
732 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
733 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
734 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
735 /* The following *CCGR6* exist only on i.MX6SX */
736 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
737 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
738 #define MXC_CCM_CCGR6_VADC_OFFSET 20
739 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
740 #define MXC_CCM_CCGR6_GIS_OFFSET 22
741 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
742 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
743 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
744 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
745 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
746 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
747 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
748 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
749 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
750 /* These two do not exist on i.MX6SX */
751 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
752 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
754 #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
755 #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
756 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
757 #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
758 #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
759 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
760 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
761 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
762 (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
763 BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
764 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
765 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
766 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
767 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
768 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
769 #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
770 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
771 #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
772 #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
773 #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
774 #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
775 #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
776 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
777 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
778 (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
779 BM_ANADIG_PLL_ARM_DIV_SELECT)
781 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
782 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
783 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
784 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
785 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
786 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
787 BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
788 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
789 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
790 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
791 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
792 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
793 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
794 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
795 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
796 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
797 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
798 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
799 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
800 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
801 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
802 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
803 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
804 BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
805 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
806 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
807 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
808 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
809 BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
811 #define BM_ANADIG_PLL_528_LOCK (1 << 31)
812 #define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
813 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
814 #define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
815 #define BM_ANADIG_PLL_528_BYPASS (1 << 16)
816 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
817 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
818 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
819 (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
820 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
821 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
822 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
823 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
824 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
825 #define BM_ANADIG_PLL_528_ENABLE (1 << 13)
826 #define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
827 #define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
828 #define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
829 #define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
830 #define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
831 #define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
832 #define BP_ANADIG_PLL_528_DIV_SELECT 0
833 #define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
834 #define BF_ANADIG_PLL_528_DIV_SELECT(v) \
835 (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
836 BM_ANADIG_PLL_528_DIV_SELECT)
838 #define BP_ANADIG_PLL_528_SS_STOP 16
839 #define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
840 #define BF_ANADIG_PLL_528_SS_STOP(v) \
841 (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
842 BM_ANADIG_PLL_528_SS_STOP)
843 #define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
844 #define BP_ANADIG_PLL_528_SS_STEP 0
845 #define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
846 #define BF_ANADIG_PLL_528_SS_STEP(v) \
847 (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
848 BM_ANADIG_PLL_528_SS_STEP)
850 #define BP_ANADIG_PLL_528_NUM_A 0
851 #define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
852 #define BF_ANADIG_PLL_528_NUM_A(v) \
853 (((v) << BP_ANADIG_PLL_528_NUM_A) & \
854 BM_ANADIG_PLL_528_NUM_A)
856 #define BP_ANADIG_PLL_528_DENOM_B 0
857 #define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
858 #define BF_ANADIG_PLL_528_DENOM_B(v) \
859 (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
860 BM_ANADIG_PLL_528_DENOM_B)
862 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
863 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
864 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
865 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
866 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
867 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
868 BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
869 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
870 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
871 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
872 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
873 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
874 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
875 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
876 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
877 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
878 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
879 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
880 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
881 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
882 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
883 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
884 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
885 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
886 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
887 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
888 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
889 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
890 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
891 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
892 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
894 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
895 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
896 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
897 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
898 BM_ANADIG_PLL_AUDIO_NUM_A)
900 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
901 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
902 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
903 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
904 BM_ANADIG_PLL_AUDIO_DENOM_B)
906 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
907 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
908 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
909 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
910 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
911 (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
912 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
913 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
914 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
915 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
916 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
917 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
918 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
919 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
920 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
921 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
922 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
923 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
924 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
925 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
926 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
927 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
928 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
929 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
930 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
931 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
932 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
933 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
934 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
935 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
936 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
938 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
939 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
940 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
941 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
942 BM_ANADIG_PLL_VIDEO_NUM_A)
944 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
945 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
946 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
947 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
948 BM_ANADIG_PLL_VIDEO_DENOM_B)
950 #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
951 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
952 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
953 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
954 (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
955 BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
956 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
957 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
958 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
959 (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
960 BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
961 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
962 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
963 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
964 (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
965 BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
966 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
967 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
968 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
969 (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
970 BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
971 #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
972 #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
973 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
974 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
975 (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
976 BM_ANADIG_PLL_MLB_PHASE_SEL)
977 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
979 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
980 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
981 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
982 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
983 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
984 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
985 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
986 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
987 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
988 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
989 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
990 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
991 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
992 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
993 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
994 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
995 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
996 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
997 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
998 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
999 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
1000 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
1001 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
1002 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1003 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
1004 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1005 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
1006 BM_ANADIG_PLL_ENET_DIV_SELECT)
1008 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
1009 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
1010 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1011 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
1012 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1013 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
1014 BM_ANADIG_PFD_480_PFD3_FRAC)
1015 #define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
1016 #define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
1017 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1018 #define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
1019 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1020 (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
1021 BM_ANADIG_PFD_480_PFD2_FRAC)
1022 #define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
1023 #define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
1024 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1025 #define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
1026 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1027 (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
1028 BM_ANADIG_PFD_480_PFD1_FRAC)
1029 #define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
1030 #define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
1031 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1032 #define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
1033 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1034 (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
1035 BM_ANADIG_PFD_480_PFD0_FRAC)
1037 #define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
1038 #define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
1039 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1040 #define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
1041 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1042 (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
1043 BM_ANADIG_PFD_528_PFD3_FRAC)
1044 #define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
1045 #define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
1046 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1047 #define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
1048 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1049 (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
1050 BM_ANADIG_PFD_528_PFD2_FRAC)
1051 #define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
1052 #define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
1053 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1054 #define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
1055 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1056 (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
1057 BM_ANADIG_PFD_528_PFD1_FRAC)
1058 #define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
1059 #define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
1060 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1061 #define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
1062 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1063 (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
1064 BM_ANADIG_PFD_528_PFD0_FRAC)
1066 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
1067 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1068 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
1069 (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
1070 BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1071 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
1072 #define BP_ANADIG_ANA_MISC0_ANAMUX 21
1073 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
1074 #define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
1075 (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
1076 BM_ANADIG_ANA_MISC0_ANAMUX)
1077 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
1078 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
1079 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1080 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
1081 (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
1082 BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1083 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
1084 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
1085 #define BP_ANADIG_ANA_MISC0_OSC_I 14
1086 #define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
1087 #define BF_ANADIG_ANA_MISC0_OSC_I(v) \
1088 (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
1089 BM_ANADIG_ANA_MISC0_OSC_I)
1090 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
1091 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
1092 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
1093 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1094 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
1095 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
1096 BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1097 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
1098 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
1099 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1100 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
1101 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
1102 BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1103 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
1104 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
1105 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
1106 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
1108 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
1109 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
1110 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
1111 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
1112 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1113 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
1114 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1115 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
1116 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1117 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
1118 (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
1119 BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1120 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
1121 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1122 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
1123 (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
1124 BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1126 #define BP_ANADIG_ANA_MISC2_CONTROL3 30
1127 #define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
1128 #define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
1129 (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
1130 BM_ANADIG_ANA_MISC2_CONTROL3)
1131 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
1132 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1133 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
1134 (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
1135 BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1136 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
1137 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1138 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
1139 (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
1140 BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1141 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
1142 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1143 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
1144 (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
1145 BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1146 #define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
1147 #define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
1148 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
1149 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
1150 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
1151 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1152 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
1153 (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
1154 BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1155 #define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
1156 #define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
1157 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
1158 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
1159 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
1160 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
1161 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
1162 (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
1163 BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
1164 #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
1165 #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
1166 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
1167 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
1168 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
1169 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1170 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
1171 (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
1172 BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1174 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
1175 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
1176 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
1177 (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
1178 BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
1179 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
1180 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
1181 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
1182 (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
1183 BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
1184 #define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
1185 #define BP_ANADIG_TEMPSENSE0_VBGADJ 3
1186 #define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
1187 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
1188 (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
1189 BM_ANADIG_TEMPSENSE0_VBGADJ)
1190 #define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
1191 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
1192 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
1194 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
1195 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1196 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
1197 (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
1198 BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1201 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */