acb1136372a81153f0458da170706356e7dacbc9
[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / crm_regs.h
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
9
10 #define CCM_CCOSR               0x020c4060
11 #define CCM_CCGR0               0x020C4068
12 #define CCM_CCGR1               0x020C406c
13 #define CCM_CCGR2               0x020C4070
14 #define CCM_CCGR3               0x020C4074
15 #define CCM_CCGR4               0x020C4078
16 #define CCM_CCGR5               0x020C407c
17 #define CCM_CCGR6               0x020C4080
18
19 #define PMU_MISC2               0x020C8170
20
21 #ifndef __ASSEMBLY__
22 struct mxc_ccm_reg {
23         u32 ccr;        /* 0x0000 */
24         u32 ccdr;
25         u32 csr;
26         u32 ccsr;
27         u32 cacrr;      /* 0x0010*/
28         u32 cbcdr;
29         u32 cbcmr;
30         u32 cscmr1;
31         u32 cscmr2;     /* 0x0020 */
32         u32 cscdr1;
33         u32 cs1cdr;
34         u32 cs2cdr;
35         u32 cdcdr;      /* 0x0030 */
36         u32 chsccdr;
37         u32 cscdr2;
38         u32 cscdr3;
39         u32 cscdr4;     /* 0x0040 */
40         u32 resv0;
41         u32 cdhipr;
42         u32 cdcr;
43         u32 ctor;       /* 0x0050 */
44         u32 clpcr;
45         u32 cisr;
46         u32 cimr;
47         u32 ccosr;      /* 0x0060 */
48         u32 cgpr;
49         u32 CCGR0;
50         u32 CCGR1;
51         u32 CCGR2;      /* 0x0070 */
52         u32 CCGR3;
53         u32 CCGR4;
54         u32 CCGR5;
55         u32 CCGR6;      /* 0x0080 */
56         u32 CCGR7;
57         u32 cmeor;
58 };
59 #endif
60
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN                              (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                 (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET               21
65 /* CCR_WB does not exist on i.MX6SX/UL */
66 #define MXC_CCM_CCR_WB_COUNT_MASK                       (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
67 #define MXC_CCM_CCR_WB_COUNT_OFFSET                     (1 << 16)
68 #define MXC_CCM_CCR_COSC_EN                             (1 << 12)
69 #ifdef CONFIG_SOC_MX6SX
70 #define MXC_CCM_CCR_OSCNT_MASK                          0x7F
71 #else
72 #define MXC_CCM_CCR_OSCNT_MASK                          0xFF
73 #endif
74 #define MXC_CCM_CCR_OSCNT_OFFSET                        0
75
76 /* Define the bits in register CCDR */
77 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                   (1 << 16)
78 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                   (1 << 17)
79 /* Exists on i.MX6QP */
80 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG               (1 << 18)
81
82 /* Define the bits in register CSR */
83 #define MXC_CCM_CSR_COSC_READY                          (1 << 5)
84 #define MXC_CCM_CSR_REF_EN_B                            (1 << 0)
85
86 /* Define the bits in register CCSR */
87 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS                  (1 << 15)
88 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS                  (1 << 14)
89 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS                  (1 << 13)
90 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS                  (1 << 12)
91 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS                  (1 << 11)
92 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS                  (1 << 10)
93 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS                  (1 << 9)
94 #define MXC_CCM_CCSR_STEP_SEL                           (1 << 8)
95 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL                    (1 << 2)
96 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL                    (1 << 1)
97 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL                    (1 << 0)
98
99 /* Define the bits in register CACRR */
100 #define MXC_CCM_CACRR_ARM_PODF_OFFSET                   0
101 #define MXC_CCM_CACRR_ARM_PODF_MASK                     (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
102
103 /* Define the bits in register CBCDR */
104 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK             (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
105 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET           27
106 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL                   (1 << 26)
107 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                    (1 << 25)
108 /* MMDC_CH0 not exists on i.MX6SX */
109 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK                (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
110 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET              19
111 #define MXC_CCM_CBCDR_AXI_PODF_MASK                     (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET                   16
113 #define MXC_CCM_CBCDR_AHB_PODF_MASK                     (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET                   10
115 #define MXC_CCM_CBCDR_IPG_PODF_MASK                     (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
116 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET                   8
117 #define MXC_CCM_CBCDR_AXI_ALT_SEL                       (1 << 7)
118 #define MXC_CCM_CBCDR_AXI_SEL                           (1 << 6)
119 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK                (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
120 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET              3
121 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK            (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
122 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET          0
123
124 /* Define the bits in register CBCMR */
125 #if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
126 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK            (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
127 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET          29
128 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK              (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
129 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET            26
130 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK              (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
131 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET            23
132 #else
133 #define MXC_CCM_CBCMR_LCDIF_PODF_MASK                   (0x7 << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET)
134 #define MXC_CCM_CBCMR_LCDIF_PODF_OFFSET                 23
135 #endif
136 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
137 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET        21
138 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL                  (1 << 20)
139 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK           (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
140 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET         18
141 #ifndef CONFIG_SOC_MX6SX
142 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK                (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
143 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET              16
144 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK              (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
145 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET            14
146 #endif
147 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK              (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
148 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET            12
149 #ifndef CONFIG_SOC_MX6SX
150 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                    (1 << 11)
151 #endif
152 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                  (1 << 10)
153 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK         (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
154 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET       8
155 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK           (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
156 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET         4
157 /* Exists on i.MX6QP */
158 #define MXC_CCM_CBCMR_PRE_CLK_SEL                       (1 << 1)
159
160 /* Define the bits in register CSCMR1 */
161 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK               (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
162 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET             29
163 /* QSPI1 exist on i.MX6SX/UL */
164 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                  (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
165 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET                26
166 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK                    (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
167 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                  27
168 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK          (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
169 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET        23
170 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
171 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK               (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
172 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET             20
173 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
174 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL                     (1 << 19)
175 #define MXC_CCM_CSCMR1_BCH_CLK_SEL                      (1 << 18)
176 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                   (1 << 19)
177 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                   (1 << 18)
178 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                   (1 << 17)
179 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL                   (1 << 16)
180 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK                (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
181 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET              14
182 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK                (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
183 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              12
184 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
185 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              10
186 /* QSPI1 exist on i.MX6SX/UL */
187 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK               (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
188 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET             7
189 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
190 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                 (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
191 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET               6
192
193 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                 0x3F
194
195 /* Define the bits in register CSCMR2 */
196 #ifdef CONFIG_SOC_MX6SX
197 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                 (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
198 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET               21
199 #endif
200 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK                (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
201 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET              19
202 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                  (1 << 11)
203 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                  (1 << 10)
204 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
205 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                 (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
206 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET               8
207
208 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK                (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
209 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET              2
210
211 /* Define the bits in register CSCDR1 */
212 #ifndef CONFIG_SOC_MX6SX
213 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK                (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
214 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET              25
215 #endif
216 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
217 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK                   (0x7 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)
218 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET                 22
219 #define MXC_CCM_CSCDR1_BCH_PODF_MASK                    (0x7 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET)
220 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET                  19
221
222 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
223 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET               22
224 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
225 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET               19
226 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
227 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET               16
228 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
229 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET               11
230 #ifndef CONFIG_SOC_MX6SX
231 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET           8
232 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK             (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
233 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET           6
234 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK             (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
235 #endif
236 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
237 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET             0
238 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
239 #define MXC_CCM_CSCDR1_UART_CLK_SEL                     (1 << 6)
240
241 /* Define the bits in register CS1CDR */
242 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK               (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
243 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET             25
244 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK               (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
245 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET             22
246 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK               (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
247 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET             16
248 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK               (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
249 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET             9
250 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK               (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
251 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET             6
252 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK               (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
253 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET             0
254
255 /* Define the bits in register CS2CDR */
256 /* QSPI2 on i.MX6SX */
257 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK              (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
258 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET            21
259 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
260 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK              (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
261 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET            18
262 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
263 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK               (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
264 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET             15
265 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                 (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
266
267 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK               (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
268 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET             21
269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                 (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
270 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK               (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
271 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET             18
272 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                 (((v) & 0x7) << 18)
273
274 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP            (0x7 << 15)
275 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP          15
276 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v)              (((v) & 0x7) << 15)
277 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ             (0x3 << 16)
278 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ           16
279 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)               (((v) & 0x3) << 16)
280
281 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK                \
282         ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
283          MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :         \
284          MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
285 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET              \
286         ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
287          MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :       \
288          MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
289 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                  \
290         ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
291          MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :           \
292          MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
293
294 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK             (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
295 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET           12
296 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK             (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
297 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET           9
298 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK               (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
299 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET             6
300 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK               (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
301 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET             0
302
303 /* Define the bits in register CDCDR */
304 #ifndef CONFIG_SOC_MX6SX
305 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                  (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
306 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET                29
307 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK               (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
308 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET             28
309 #endif
310 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
311 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET            25
312 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
313 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET            22
314 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK               (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
315 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET             20
316 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
317 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET            12
318 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
319 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET            9
320 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK               (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
321 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET             7
322
323 /* Define the bits in register CHSCCDR */
324 #ifdef CONFIG_SOC_MX6SX
325 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
326 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET         15
327 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                  (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
328 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET                12
329 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK               (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
330 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET             9
331 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK             (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
332 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET           6
333 #define MXC_CCM_CHSCCDR_M4_PODF_MASK                    (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
334 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET                  3
335 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                 (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
336 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET               0
337 #else
338 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
339 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET     15
340 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK              (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
341 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET            12
342 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
343 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET         9
344 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
345 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET     6
346 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK              (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
347 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET            3
348 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
349 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET         0
350 #endif
351
352 #define CHSCCDR_CLK_SEL_LDB_DI0                         3
353 #define CHSCCDR_PODF_DIVIDE_BY_3                        2
354 #define CHSCCDR_IPU_PRE_CLK_540M_PFD                    5
355
356 /* Define the bits in register CSCDR2 */
357 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
358 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET            19
359 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
360 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK               (0x1 << 18)
361
362 /* All IPU2_DI1 are LCDIF1 on MX6SX */
363 #if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
364 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK        (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
365 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET      15
366 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK               (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
367 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET             12
368 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK            (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
369 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET          9
370 #else
371 #define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK           (0x7 << MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET)
372 #define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET         15
373 #define MXC_CCM_CSCDR2_LCDIF_PRED_MASK                  (0x7 << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET)
374 #define MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET                12
375 #define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK               (0x7 << MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET)
376 #define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET             9
377 #endif
378 /* All IPU2_DI0 are LCDIF2 on MX6SX */
379 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK        (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
380 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET      6
381 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK               (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
382 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET             3
383 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK            (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
384 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET          0
385
386 /* Define the bits in register CSCDR3 */
387 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK               (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
388 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET             16
389 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK            (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
390 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET          14
391 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK               (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
392 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET             11
393 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK            (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
394 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET          9
395
396 /* Define the bits in register CDHIPR */
397 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY                    (1 << 16)
398 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY              (1 << 5)
399 #ifndef CONFIG_SOC_MX6SX
400 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY               (1 << 4)
401 #endif
402 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY             (1 << 3)
403 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY               (1 << 2)
404 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY                    (1 << 1)
405 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY                    (1 << 0)
406
407 /* Define the bits in register CLPCR */
408 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE                    (1 << 27)
409 #define MXC_CCM_CLPCR_MASK_SCU_IDLE                     (1 << 26)
410 #ifndef CONFIG_SOC_MX6SX
411 #define MXC_CCM_CLPCR_MASK_CORE3_WFI                    (1 << 25)
412 #define MXC_CCM_CLPCR_MASK_CORE2_WFI                    (1 << 24)
413 #define MXC_CCM_CLPCR_MASK_CORE1_WFI                    (1 << 23)
414 #endif
415 #define MXC_CCM_CLPCR_MASK_CORE0_WFI                    (1 << 22)
416 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS               (1 << 21)
417 #ifndef CONFIG_SOC_MX6SX
418 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS               (1 << 19)
419 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                    (1 << 17)
420 #endif
421 #define MXC_CCM_CLPCR_WB_PER_AT_LPM                     (1 << 16)
422 #define MXC_CCM_CLPCR_COSC_PWRDOWN                      (1 << 11)
423 #define MXC_CCM_CLPCR_STBY_COUNT_MASK                   (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
424 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                 9
425 #define MXC_CCM_CLPCR_VSTBY                             (1 << 8)
426 #define MXC_CCM_CLPCR_DIS_REF_OSC                       (1 << 7)
427 #define MXC_CCM_CLPCR_SBYOS                             (1 << 6)
428 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM                (1 << 5)
429 #ifndef CONFIG_SOC_MX6SX
430 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                 (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
431 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET               3
432 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY           (1 << 2)
433 #endif
434 #define MXC_CCM_CLPCR_LPM_MASK                          (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
435 #define MXC_CCM_CLPCR_LPM_OFFSET                        0
436
437 /* Define the bits in register CISR */
438 #define MXC_CCM_CISR_ARM_PODF_LOADED                    (1 << 26)
439 #ifndef CONFIG_SOC_MX6SX
440 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED               (1 << 23)
441 #endif
442 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED              (1 << 22)
443 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED               (1 << 21)
444 #define MXC_CCM_CISR_AHB_PODF_LOADED                    (1 << 20)
445 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED             (1 << 19)
446 #define MXC_CCM_CISR_AXI_PODF_LOADED                    (1 << 17)
447 #define MXC_CCM_CISR_COSC_READY                         (1 << 6)
448 #define MXC_CCM_CISR_LRF_PLL                            (1 << 0)
449
450 /* Define the bits in register CIMR */
451 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED               (1 << 26)
452 #ifndef CONFIG_SOC_MX6SX
453 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED          (1 << 23)
454 #endif
455 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED         (1 << 22)
456 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED          (1 << 21)
457 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED               (1 << 20)
458 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED        (1 << 19)
459 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED               (1 << 17)
460 #define MXC_CCM_CIMR_MASK_COSC_READY                    (1 << 6)
461 #define MXC_CCM_CIMR_MASK_LRF_PLL                       (1 << 0)
462
463 /* Define the bits in register CCOSR */
464 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET                    (1 << 24)
465 #define MXC_CCM_CCOSR_CKO2_DIV_MASK                     (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
466 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                   21
467 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                   16
468 #define MXC_CCM_CCOSR_CKO2_SEL_MASK                     (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
469 #define MXC_CCM_CCOSR_CLK_OUT_SEL                       (0x1 << 8)
470 #define MXC_CCM_CCOSR_CKOL_EN                           (0x1 << 7)
471 #define MXC_CCM_CCOSR_CKOL_DIV_MASK                     (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
472 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                   4
473 #define MXC_CCM_CCOSR_CKOL_SEL_MASK                     (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
474 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                   0
475
476 /* Define the bits in registers CGPR */
477 #define MXC_CCM_CGPR_FAST_PLL_EN                        (1 << 16)
478 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE             (1 << 4)
479 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS                   (1 << 2)
480 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER                  (1 << 0)
481
482 /* Define the bits in registers CCGRx */
483 #define MXC_CCM_CCGR_CG_MASK                            3
484
485 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                   0
486 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
487 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                   2
488 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
489 #define MXC_CCM_CCGR0_APBHDMA_OFFSET                    4
490 #define MXC_CCM_CCGR0_APBHDMA_MASK                      (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
491 #define MXC_CCM_CCGR0_ASRC_OFFSET                       6
492 #define MXC_CCM_CCGR0_ASRC_MASK                         (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
493 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET            8
494 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK              (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
495 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET          10
496 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK            (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
497 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET           12
498 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK             (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
499 #define MXC_CCM_CCGR0_CAN1_OFFSET                       14
500 #define MXC_CCM_CCGR0_CAN1_MASK                         (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
501 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET                16
502 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK                  (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
503 #define MXC_CCM_CCGR0_CAN2_OFFSET                       18
504 #define MXC_CCM_CCGR0_CAN2_MASK                         (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
505 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET                20
506 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK                  (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
507 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET            22
508 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK              (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
509 #define MXC_CCM_CCGR0_DCIC1_OFFSET                      24
510 #define MXC_CCM_CCGR0_DCIC1_MASK                        (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
511 #define MXC_CCM_CCGR0_DCIC2_OFFSET                      26
512 #define MXC_CCM_CCGR0_DCIC2_MASK                        (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
513 #ifdef CONFIG_SOC_MX6SX
514 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET                   30
515 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
516 #else
517 #define MXC_CCM_CCGR0_DTCP_OFFSET                       28
518 #define MXC_CCM_CCGR0_DTCP_MASK                         (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
519 #endif
520
521 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET                    0
522 #define MXC_CCM_CCGR1_ECSPI1S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
523 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET                    2
524 #define MXC_CCM_CCGR1_ECSPI2S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
525 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET                    4
526 #define MXC_CCM_CCGR1_ECSPI3S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
527 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET                    6
528 #define MXC_CCM_CCGR1_ECSPI4S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
529 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                    8
530 #define MXC_CCM_CCGR1_ECSPI5S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
531 /* CCGR1_ENET does not exist on i.MX6SX/UL */
532 #define MXC_CCM_CCGR1_ENET_OFFSET                       10
533 #define MXC_CCM_CCGR1_ENET_MASK                         (3 << MXC_CCM_CCGR1_ENET_OFFSET)
534 #define MXC_CCM_CCGR1_EPIT1S_OFFSET                     12
535 #define MXC_CCM_CCGR1_EPIT1S_MASK                       (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
536 #define MXC_CCM_CCGR1_EPIT2S_OFFSET                     14
537 #define MXC_CCM_CCGR1_EPIT2S_MASK                       (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
538 #define MXC_CCM_CCGR1_ESAIS_OFFSET                      16
539 #define MXC_CCM_CCGR1_ESAIS_MASK                        (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
540 #ifdef CONFIG_SOC_MX6SX
541 #define MXC_CCM_CCGR1_WAKEUP_OFFSET                     18
542 #define MXC_CCM_CCGR1_WAKEUP_MASK                       (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
543 #endif
544 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET                    20
545 #define MXC_CCM_CCGR1_GPT_BUS_MASK                      (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
546 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                 22
547 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK                   (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
548 #ifndef CONFIG_SOC_MX6SX
549 #define MXC_CCM_CCGR1_GPU2D_OFFSET                      24
550 #define MXC_CCM_CCGR1_GPU2D_MASK                        (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
551 #endif
552 #define MXC_CCM_CCGR1_GPU3D_OFFSET                      26
553 #define MXC_CCM_CCGR1_GPU3D_MASK                        (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
554 #ifdef CONFIG_SOC_MX6SX
555 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET                    28
556 #define MXC_CCM_CCGR1_OCRAM_S_MASK                      (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
557 #define MXC_CCM_CCGR1_CANFD_OFFSET                      30
558 #define MXC_CCM_CCGR1_CANFD_MASK                        (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
559 #endif
560
561 #if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)
562 #define MXC_CCM_CCGR2_CSI_OFFSET                        2
563 #define MXC_CCM_CCGR2_CSI_MASK                          (3 << MXC_CCM_CCGR2_CSI_OFFSET)
564 #else
565 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET            0
566 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK              (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
567 #endif
568 #if !defined(CONFIG_SOC_MX6SX) && !defined(CONFIG_SOC_MX6UL)
569 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET            4
570 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK              (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
571 #endif
572 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET                6
573 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
574 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET                8
575 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
576 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET                10
577 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
578 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET                8
579 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
580 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                 12
581 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                   (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
582 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET           14
583 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK             (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
584 #define MXC_CCM_CCGR2_IPMUX1_OFFSET                     16
585 #define MXC_CCM_CCGR2_IPMUX1_MASK                       (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
586 #define MXC_CCM_CCGR2_IPMUX2_OFFSET                     18
587 #define MXC_CCM_CCGR2_IPMUX2_MASK                       (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
588 #define MXC_CCM_CCGR2_IPMUX3_OFFSET                     20
589 #define MXC_CCM_CCGR2_IPMUX3_MASK                       (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
590 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET  22
591 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK    (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
592 #if defined(CONFIG_SOC_MX6SX) || (CONFIG_SOC_MX6UL)
593 #define MXC_CCM_CCGR2_LCD_OFFSET                        28
594 #define MXC_CCM_CCGR2_LCD_MASK                          (3 << MXC_CCM_CCGR2_LCD_OFFSET)
595 #define MXC_CCM_CCGR2_PXP_OFFSET                        30
596 #define MXC_CCM_CCGR2_PXP_MASK                          (3 << MXC_CCM_CCGR2_PXP_OFFSET)
597 #else
598 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET   24
599 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK     (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
600 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
601 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
602 #endif
603
604 /* Exist on i.MX6SX */
605 #define MXC_CCM_CCGR3_M4_OFFSET                                 2
606 #define MXC_CCM_CCGR3_M4_MASK                                   (3 << MXC_CCM_CCGR3_M4_OFFSET)
607 #define MXC_CCM_CCGR3_ENET_OFFSET                               4
608 #define MXC_CCM_CCGR3_ENET_MASK                                 (3 << MXC_CCM_CCGR3_ENET_OFFSET)
609 #define MXC_CCM_CCGR3_QSPI_OFFSET                               14
610 #define MXC_CCM_CCGR3_QSPI_MASK                                 (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
611
612 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET                           0
613 #define MXC_CCM_CCGR3_IPU1_IPU_MASK                             (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
614 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET                       2
615 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                         (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
616 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET                       4
617 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                         (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
618
619 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET                           6
620 #define MXC_CCM_CCGR3_IPU2_IPU_MASK                             (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
621 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET                       8
622 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK                         (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
623 /* IPU2_DI1 on i.MX6Q, i.MX6DL */
624 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET                       10
625 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                         (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
626 /* LCDIF on i.MX6UL */
627 #define MXC_CCM_CCGR3_LCDIF_OFFSET                              10
628 #define MXC_CCM_CCGR3_LCDIF_MASK                                (3 << MXC_CCM_CCGR3_LCDIF_OFFSET)
629
630 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                            12
631 #define MXC_CCM_CCGR3_LDB_DI0_MASK                              (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
632
633 /* QSPI1 exists on i.MX6SX/UL */
634 #define MXC_CCM_CCGR3_QSPI1_OFFSET                              14
635 #define MXC_CCM_CCGR3_QSPI1_MASK                                (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
636
637 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET                            14
638 #define MXC_CCM_CCGR3_LDB_DI1_MASK                              (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
639 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET                      16
640 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                        (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
641
642 /* A7_CLKDIV/WDOG1 on i.MX6UL */
643 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET                   16
644 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK                     (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
645 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET                    18
646 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK                      (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
647
648 #define MXC_CCM_CCGR3_MLB_OFFSET                                18
649 #define MXC_CCM_CCGR3_MLB_MASK                                  (3 << MXC_CCM_CCGR3_MLB_OFFSET)
650 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET        20
651 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK          (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
652 #ifndef CONFIG_SOC_MX6SX
653 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET        22
654 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK          (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
655 #endif
656 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET               24
657 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                 (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
658 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET               26
659 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                 (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
660 /* AXI on i.MX6UL */
661 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET                            28
662 #define MXC_CCM_CCGR3_AXI_CLK_MASK                              (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
663 #define MXC_CCM_CCGR3_OCRAM_OFFSET                              28
664 #define MXC_CCM_CCGR3_OCRAM_MASK                                (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
665
666 /* GPIO4 on i.MX6UL */
667 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET                          30
668 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK                            (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
669
670 #ifndef CONFIG_MX6SX
671 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                       30
672 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                         (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
673 #endif
674
675 #define MXC_CCM_CCGR4_PCIE_OFFSET                               0
676 #define MXC_CCM_CCGR4_PCIE_MASK                                 (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
677 /* QSPI2 on i.MX6SX */
678 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                         10
679 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                           (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
680 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET               8
681 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                 (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
682 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET                 12
683 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                   (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
684 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET      14
685 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK        (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
686 #define MXC_CCM_CCGR4_PWM1_OFFSET                               16
687 #define MXC_CCM_CCGR4_PWM1_MASK                                 (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
688 #define MXC_CCM_CCGR4_PWM2_OFFSET                               18
689 #define MXC_CCM_CCGR4_PWM2_MASK                                 (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
690 #define MXC_CCM_CCGR4_PWM3_OFFSET                               20
691 #define MXC_CCM_CCGR4_PWM3_MASK                                 (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
692 #define MXC_CCM_CCGR4_PWM4_OFFSET                               22
693 #define MXC_CCM_CCGR4_PWM4_MASK                                 (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
694 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET            24
695 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK              (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
696 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET       26
697 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK         (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
698 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET   28
699 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK     (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
700 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET           30
701 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK             (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
702
703 #define MXC_CCM_CCGR5_ROM_OFFSET                                0
704 #define MXC_CCM_CCGR5_ROM_MASK                                  (3 << MXC_CCM_CCGR5_ROM_OFFSET)
705 #ifndef CONFIG_SOC_MX6SX
706 #define MXC_CCM_CCGR5_SATA_OFFSET                               4
707 #define MXC_CCM_CCGR5_SATA_MASK                                 (3 << MXC_CCM_CCGR5_SATA_OFFSET)
708 #endif
709 #define MXC_CCM_CCGR5_SDMA_OFFSET                               6
710 #define MXC_CCM_CCGR5_SDMA_MASK                                 (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
711 #define MXC_CCM_CCGR5_SPBA_OFFSET                               12
712 #define MXC_CCM_CCGR5_SPBA_MASK                                 (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
713 #define MXC_CCM_CCGR5_SPDIF_OFFSET                              14
714 #define MXC_CCM_CCGR5_SPDIF_MASK                                (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
715 #define MXC_CCM_CCGR5_SSI1_OFFSET                               18
716 #define MXC_CCM_CCGR5_SSI1_MASK                                 (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
717 #define MXC_CCM_CCGR5_SSI2_OFFSET                               20
718 #define MXC_CCM_CCGR5_SSI2_MASK                                 (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
719 #define MXC_CCM_CCGR5_SSI3_OFFSET                               22
720 #define MXC_CCM_CCGR5_SSI3_MASK                                 (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
721 #define MXC_CCM_CCGR5_UART_OFFSET                               24
722 #define MXC_CCM_CCGR5_UART_MASK                                 (3 << MXC_CCM_CCGR5_UART_OFFSET)
723 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET                        26
724 #define MXC_CCM_CCGR5_UART_SERIAL_MASK                          (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
725 #ifdef CONFIG_SOC_MX6SX
726 #define MXC_CCM_CCGR5_SAI1_OFFSET                               20
727 #define MXC_CCM_CCGR5_SAI1_MASK                                 (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
728 #define MXC_CCM_CCGR5_SAI2_OFFSET                               30
729 #define MXC_CCM_CCGR5_SAI2_MASK                                 (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
730 #endif
731
732 /* PRG_CLK0 exists on i.MX6QP */
733 #define MXC_CCM_CCGR6_PRG_CLK0_OFFSET                           24
734 #define MXC_CCM_CCGR6_PRG_CLK0_MASK                             (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
735
736 #define MXC_CCM_CCGR6_USBOH3_OFFSET                             0
737 #define MXC_CCM_CCGR6_USBOH3_MASK                               (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
738 #define MXC_CCM_CCGR6_USDHC1_OFFSET                             2
739 #define MXC_CCM_CCGR6_USDHC1_MASK                               (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
740 #define MXC_CCM_CCGR6_USDHC2_OFFSET                             4
741 #define MXC_CCM_CCGR6_USDHC2_MASK                               (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
742 /* GPMI/BCH on i.MX6UL */
743 #define MXC_CCM_CCGR6_BCH_OFFSET                                6
744 #define MXC_CCM_CCGR6_BCH_MASK                                  (3 << MXC_CCM_CCGR6_BCH_OFFSET)
745 #define MXC_CCM_CCGR6_GPMI_OFFSET                               8
746 #define MXC_CCM_CCGR6_GPMI_MASK                                 (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
747
748 #define MXC_CCM_CCGR6_USDHC3_OFFSET                             6
749 #define MXC_CCM_CCGR6_USDHC3_MASK                               (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
750 #define MXC_CCM_CCGR6_USDHC4_OFFSET                             8
751 #define MXC_CCM_CCGR6_USDHC4_MASK                               (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
752 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                           10
753 #define MXC_CCM_CCGR6_EMI_SLOW_MASK                             (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
754 /* The following *CCGR6* exist only on i.MX6SX */
755 #define MXC_CCM_CCGR6_PWM8_OFFSET                               16
756 #define MXC_CCM_CCGR6_PWM8_MASK                                 (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
757 #define MXC_CCM_CCGR6_VADC_OFFSET                               20
758 #define MXC_CCM_CCGR6_VADC_MASK                                 (3 << MXC_CCM_CCGR6_VADC_OFFSET)
759 #define MXC_CCM_CCGR6_GIS_OFFSET                                22
760 #define MXC_CCM_CCGR6_GIS_MASK                                  (3 << MXC_CCM_CCGR6_GIS_OFFSET)
761 #define MXC_CCM_CCGR6_I2C4_OFFSET                               24
762 #define MXC_CCM_CCGR6_I2C4_MASK                                 (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
763 #define MXC_CCM_CCGR6_PWM5_OFFSET                               26
764 #define MXC_CCM_CCGR6_PWM5_MASK                                 (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
765 #define MXC_CCM_CCGR6_PWM6_OFFSET                               28
766 #define MXC_CCM_CCGR6_PWM6_MASK                                 (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
767 #define MXC_CCM_CCGR6_PWM7_OFFSET                               30
768 #define MXC_CCM_CCGR6_PWM7_MASK                                 (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
769 /* These two do not exist on i.MX6SX */
770 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                          12
771 #define MXC_CCM_CCGR6_VDOAXICLK_MASK                            (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
772
773 #define BM_ANADIG_PLL_ARM_LOCK                                  (1 << 31)
774 #define BM_ANADIG_PLL_ARM_PLL_SEL                               (1 << 19)
775 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL                        (1 << 18)
776 #define BM_ANADIG_PLL_ARM_LVDS_SEL                              (1 << 17)
777 #define BM_ANADIG_PLL_ARM_BYPASS                                (1 << 16)
778 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC                        14
779 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC                        (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
780 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v)          \
781         (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
782                 BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
783 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M               0x0
784 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1              0x1
785 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2              0x2
786 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR                   0x3
787 #define BM_ANADIG_PLL_ARM_ENABLE                                (1 << 13)
788 #define BM_ANADIG_PLL_ARM_POWERDOWN                             (1 << 12)
789 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF                         (1 << 11)
790 #define BM_ANADIG_PLL_ARM_DOUBLE_CP                             (1 << 10)
791 #define BM_ANADIG_PLL_ARM_HALF_CP                               (1 << 9)
792 #define BM_ANADIG_PLL_ARM_DOUBLE_LF                             (1 << 8)
793 #define BM_ANADIG_PLL_ARM_HALF_LF                               (1 << 7)
794 #define BP_ANADIG_PLL_ARM_DIV_SELECT                            0
795 #define BM_ANADIG_PLL_ARM_DIV_SELECT                            (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
796 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v)          \
797         (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
798                 BM_ANADIG_PLL_ARM_DIV_SELECT)
799
800 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK                                (1 << 31)
801 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS                      (1 << 16)
802 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC              14
803 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC              (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
804 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)           \
805         (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) &  \
806                 BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
807 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M     0x0
808 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1    0x1
809 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2    0x2
810 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR         0x3
811 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE                      (1 << 13)
812 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER                       (1 << 12)
813 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF               (1 << 11)
814 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP                   (1 << 10)
815 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP                     (1 << 9)
816 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF                   (1 << 8)
817 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF                     (1 << 7)
818 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS                 (1 << 6)
819 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0                    2
820 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0                    (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
821 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)         \
822         (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
823                 BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
824 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT                  0
825 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT                  (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
826 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)          \
827         (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
828                 BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
829
830 #define BM_ANADIG_PLL_528_LOCK                                  (1 << 31)
831 #define BM_ANADIG_PLL_528_PLL_SEL                               (1 << 19)
832 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL                        (1 << 18)
833 #define BM_ANADIG_PLL_528_LVDS_SEL                              (1 << 17)
834 #define BM_ANADIG_PLL_528_BYPASS                                (1 << 16)
835 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC                        14
836 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC                        (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
837 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)          \
838         (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
839                 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
840 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M               0x0
841 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1              0x1
842 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2              0x2
843 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR                   0x3
844 #define BM_ANADIG_PLL_528_ENABLE                                (1 << 13)
845 #define BM_ANADIG_PLL_528_POWERDOWN                             (1 << 12)
846 #define BM_ANADIG_PLL_528_HOLD_RING_OFF                         (1 << 11)
847 #define BM_ANADIG_PLL_528_DOUBLE_CP                             (1 << 10)
848 #define BM_ANADIG_PLL_528_HALF_CP                               (1 << 9)
849 #define BM_ANADIG_PLL_528_DOUBLE_LF                             (1 << 8)
850 #define BM_ANADIG_PLL_528_HALF_LF                               (1 << 7)
851 #define BP_ANADIG_PLL_528_DIV_SELECT                            0
852 #define BM_ANADIG_PLL_528_DIV_SELECT                            (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
853 #define BF_ANADIG_PLL_528_DIV_SELECT(v)          \
854         (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
855                 BM_ANADIG_PLL_528_DIV_SELECT)
856
857 #define BP_ANADIG_PLL_528_SS_STOP                               16
858 #define BM_ANADIG_PLL_528_SS_STOP                               (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
859 #define BF_ANADIG_PLL_528_SS_STOP(v)          \
860         (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
861                 BM_ANADIG_PLL_528_SS_STOP)
862 #define BM_ANADIG_PLL_528_SS_ENABLE                             (1 << 15)
863 #define BP_ANADIG_PLL_528_SS_STEP                               0
864 #define BM_ANADIG_PLL_528_SS_STEP                               (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
865 #define BF_ANADIG_PLL_528_SS_STEP(v)          \
866         (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
867                 BM_ANADIG_PLL_528_SS_STEP)
868
869 #define BP_ANADIG_PLL_528_NUM_A                                 0
870 #define BM_ANADIG_PLL_528_NUM_A                                 (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
871 #define BF_ANADIG_PLL_528_NUM_A(v)          \
872         (((v) << BP_ANADIG_PLL_528_NUM_A) & \
873                 BM_ANADIG_PLL_528_NUM_A)
874
875 #define BP_ANADIG_PLL_528_DENOM_B                               0
876 #define BM_ANADIG_PLL_528_DENOM_B                               (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
877 #define BF_ANADIG_PLL_528_DENOM_B(v)          \
878         (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
879                 BM_ANADIG_PLL_528_DENOM_B)
880
881 #define BM_ANADIG_PLL_AUDIO_LOCK                                (1 << 31)
882 #define BM_ANADIG_PLL_AUDIO_SSC_EN                              (1 << 21)
883 #define BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT                     19
884 #define BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT                     (0x3 << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
885 #define BF_ANADIG_PLL_AUDIO_POST_DIV_SELECT(v)          \
886         (((v) << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT) & \
887                 BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
888 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN                       (1 << 18)
889 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE                       (1 << 17)
890 #define BM_ANADIG_PLL_AUDIO_BYPASS                              (1 << 16)
891 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC                      14
892 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC                      (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
893 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)          \
894         (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
895                 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
896 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M             0x0
897 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1            0x1
898 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2            0x2
899 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR                 0x3
900 #define BM_ANADIG_PLL_AUDIO_ENABLE                              (1 << 13)
901 #define BM_ANADIG_PLL_AUDIO_POWERDOWN                           (1 << 12)
902 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF                       (1 << 11)
903 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP                           (1 << 10)
904 #define BM_ANADIG_PLL_AUDIO_HALF_CP                             (1 << 9)
905 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF                           (1 << 8)
906 #define BM_ANADIG_PLL_AUDIO_HALF_LF                             (1 << 7)
907 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT                          0
908 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT                          (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
909 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)          \
910         (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
911                 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
912
913 #define BP_ANADIG_PLL_AUDIO_NUM_A                               0
914 #define BM_ANADIG_PLL_AUDIO_NUM_A                               (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
915 #define BF_ANADIG_PLL_AUDIO_NUM_A(v)          \
916         (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
917                 BM_ANADIG_PLL_AUDIO_NUM_A)
918
919 #define BP_ANADIG_PLL_AUDIO_DENOM_B                             0
920 #define BM_ANADIG_PLL_AUDIO_DENOM_B                             (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
921 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v)          \
922         (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
923                 BM_ANADIG_PLL_AUDIO_DENOM_B)
924
925 #define BM_ANADIG_PLL_VIDEO_LOCK                                (1 << 31)
926 #define BM_ANADIG_PLL_VIDEO_SSC_EN                              (1 << 21)
927 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT                     19
928 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT                     (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
929 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)          \
930         (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
931                 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
932 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN                       (1 << 18)
933 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE                       (1 << 17)
934 #define BM_ANADIG_PLL_VIDEO_BYPASS                              (1 << 16)
935 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC                      14
936 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC                      (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
937 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)          \
938         (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
939                 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
940 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M             0x0
941 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1            0x1
942 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2            0x2
943 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR                 0x3
944 #define BM_ANADIG_PLL_VIDEO_ENABLE                              (1 << 13)
945 #define BM_ANADIG_PLL_VIDEO_POWERDOWN                           (1 << 12)
946 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF                       (1 << 11)
947 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP                           (1 << 10)
948 #define BM_ANADIG_PLL_VIDEO_HALF_CP                             (1 << 9)
949 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF                           (1 << 8)
950 #define BM_ANADIG_PLL_VIDEO_HALF_LF                             (1 << 7)
951 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT                          0
952 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT                          (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
953 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)          \
954         (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
955                 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
956
957 #define BP_ANADIG_PLL_VIDEO_NUM_A                               0
958 #define BM_ANADIG_PLL_VIDEO_NUM_A                               (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
959 #define BF_ANADIG_PLL_VIDEO_NUM_A(v)          \
960         (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
961                 BM_ANADIG_PLL_VIDEO_NUM_A)
962
963 #define BP_ANADIG_PLL_VIDEO_DENOM_B                             0
964 #define BM_ANADIG_PLL_VIDEO_DENOM_B                             (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
965 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v)          \
966         (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
967                 BM_ANADIG_PLL_VIDEO_DENOM_B)
968
969 #define BM_ANADIG_PLL_MLB_LOCK                                  (1 << 31)
970 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG                   26
971 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG                   (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
972 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v)          \
973         (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
974                 BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
975 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG                        23
976 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG                        (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
977 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v)          \
978         (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
979                 BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
980 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG                          20
981 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG                          (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
982 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v)          \
983         (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
984                 BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
985 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG                          17
986 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG                          (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
987 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v)          \
988         (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
989                 BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
990 #define BM_ANADIG_PLL_MLB_BYPASS                                (1 << 16)
991 #define BP_ANADIG_PLL_MLB_PHASE_SEL                             12
992 #define BM_ANADIG_PLL_MLB_PHASE_SEL                             (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
993 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v)          \
994         (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
995                 BM_ANADIG_PLL_MLB_PHASE_SEL)
996 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF                         (1 << 11)
997
998 #define BM_ANADIG_PLL_ENET_LOCK                                 (1 << 31)
999 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE                       (1 << 21)
1000 #define BM_ANADIG_PLL_ENET_ENABLE_SATA                          (1 << 20)
1001 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE                          (1 << 19)
1002 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN                        (1 << 18)
1003 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE                        (1 << 17)
1004 #define BM_ANADIG_PLL_ENET_BYPASS                               (1 << 16)
1005 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC                       14
1006 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC                       (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1007 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)          \
1008         (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
1009                 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1010 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M              0x0
1011 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1             0x1
1012 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2             0x2
1013 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR                  0x3
1014 #define BM_ANADIG_PLL_ENET_ENABLE                               (1 << 13)
1015 #define BM_ANADIG_PLL_ENET_POWERDOWN                            (1 << 12)
1016 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF                        (1 << 11)
1017 #define BM_ANADIG_PLL_ENET_DOUBLE_CP                            (1 << 10)
1018 #define BM_ANADIG_PLL_ENET_HALF_CP                              (1 << 9)
1019 #define BM_ANADIG_PLL_ENET_DOUBLE_LF                            (1 << 8)
1020 #define BM_ANADIG_PLL_ENET_HALF_LF                              (1 << 7)
1021 #define BP_ANADIG_PLL_ENET_DIV_SELECT                           0
1022 #define BM_ANADIG_PLL_ENET_DIV_SELECT                           (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
1023 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)          \
1024         (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
1025                 BM_ANADIG_PLL_ENET_DIV_SELECT)
1026
1027 #define BM_ANADIG_PFD_480_PFD3_CLKGATE                          (1 << 31)
1028 #define BM_ANADIG_PFD_480_PFD3_STABLE                           (1 << 30)
1029 #define BP_ANADIG_PFD_480_PFD3_FRAC                             24
1030 #define BM_ANADIG_PFD_480_PFD3_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
1031 #define BF_ANADIG_PFD_480_PFD3_FRAC(v)          \
1032         (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
1033                 BM_ANADIG_PFD_480_PFD3_FRAC)
1034 #define BM_ANADIG_PFD_480_PFD2_CLKGATE                          (1 << 23)
1035 #define BM_ANADIG_PFD_480_PFD2_STABLE                           (1 << 22)
1036 #define BP_ANADIG_PFD_480_PFD2_FRAC                             16
1037 #define BM_ANADIG_PFD_480_PFD2_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
1038 #define BF_ANADIG_PFD_480_PFD2_FRAC(v)          \
1039         (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
1040                 BM_ANADIG_PFD_480_PFD2_FRAC)
1041 #define BM_ANADIG_PFD_480_PFD1_CLKGATE                          (1 << 15)
1042 #define BM_ANADIG_PFD_480_PFD1_STABLE                           (1 << 14)
1043 #define BP_ANADIG_PFD_480_PFD1_FRAC                             8
1044 #define BM_ANADIG_PFD_480_PFD1_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
1045 #define BF_ANADIG_PFD_480_PFD1_FRAC(v)          \
1046         (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
1047                 BM_ANADIG_PFD_480_PFD1_FRAC)
1048 #define BM_ANADIG_PFD_480_PFD0_CLKGATE                          (1 << 7)
1049 #define BM_ANADIG_PFD_480_PFD0_STABLE                           (1 << 6)
1050 #define BP_ANADIG_PFD_480_PFD0_FRAC                             0
1051 #define BM_ANADIG_PFD_480_PFD0_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
1052 #define BF_ANADIG_PFD_480_PFD0_FRAC(v)          \
1053         (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
1054                 BM_ANADIG_PFD_480_PFD0_FRAC)
1055
1056 #define BM_ANADIG_PFD_528_PFD3_CLKGATE                          (1 << 31)
1057 #define BM_ANADIG_PFD_528_PFD3_STABLE                           (1 << 30)
1058 #define BP_ANADIG_PFD_528_PFD3_FRAC                             24
1059 #define BM_ANADIG_PFD_528_PFD3_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
1060 #define BF_ANADIG_PFD_528_PFD3_FRAC(v)          \
1061         (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
1062                 BM_ANADIG_PFD_528_PFD3_FRAC)
1063 #define BM_ANADIG_PFD_528_PFD2_CLKGATE                          (1 << 23)
1064 #define BM_ANADIG_PFD_528_PFD2_STABLE                           (1 << 22)
1065 #define BP_ANADIG_PFD_528_PFD2_FRAC                             16
1066 #define BM_ANADIG_PFD_528_PFD2_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
1067 #define BF_ANADIG_PFD_528_PFD2_FRAC(v)          \
1068         (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
1069                 BM_ANADIG_PFD_528_PFD2_FRAC)
1070 #define BM_ANADIG_PFD_528_PFD1_CLKGATE                          (1 << 15)
1071 #define BM_ANADIG_PFD_528_PFD1_STABLE                           (1 << 14)
1072 #define BP_ANADIG_PFD_528_PFD1_FRAC                             8
1073 #define BM_ANADIG_PFD_528_PFD1_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
1074 #define BF_ANADIG_PFD_528_PFD1_FRAC(v)          \
1075         (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
1076                 BM_ANADIG_PFD_528_PFD1_FRAC)
1077 #define BM_ANADIG_PFD_528_PFD0_CLKGATE                          (1 << 7)
1078 #define BM_ANADIG_PFD_528_PFD0_STABLE                           (1 << 6)
1079 #define BP_ANADIG_PFD_528_PFD0_FRAC                             0
1080 #define BM_ANADIG_PFD_528_PFD0_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
1081 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)          \
1082         (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
1083                 BM_ANADIG_PFD_528_PFD0_FRAC)
1084
1085 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY                       26
1086 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY                       (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1087 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)          \
1088         (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
1089                 BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1090 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL                        (1 << 25)
1091 #define BP_ANADIG_ANA_MISC0_ANAMUX                              21
1092 #define BM_ANADIG_ANA_MISC0_ANAMUX                              (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
1093 #define BF_ANADIG_ANA_MISC0_ANAMUX(v)          \
1094         (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
1095                 BM_ANADIG_ANA_MISC0_ANAMUX)
1096 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN                           (1 << 20)
1097 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH                     18
1098 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH                     (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1099 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)          \
1100         (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
1101                 BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1102 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN                       (1 << 17)
1103 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK                          (1 << 16)
1104 #define BP_ANADIG_ANA_MISC0_OSC_I                               14
1105 #define BM_ANADIG_ANA_MISC0_OSC_I                               (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
1106 #define BF_ANADIG_ANA_MISC0_OSC_I(v)          \
1107         (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
1108                 BM_ANADIG_ANA_MISC0_OSC_I)
1109 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN                      (1 << 13)
1110 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG                    (1 << 12)
1111 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST                     8
1112 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST                     (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1113 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)          \
1114         (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
1115                 BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1116 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP                        (1 << 7)
1117 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ                       4
1118 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ                       (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1119 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)          \
1120         (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
1121                 BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1122 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF                   (1 << 3)
1123 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER                     (1 << 2)
1124 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP                     (1 << 1)
1125 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD                          (1 << 0)
1126
1127 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO                          (1 << 31)
1128 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO                          (1 << 30)
1129 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO                    (1 << 29)
1130 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN                       (1 << 13)
1131 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN                       (1 << 12)
1132 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN                       (1 << 11)
1133 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN                       (1 << 10)
1134 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL                       5
1135 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL                       (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1136 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v)          \
1137         (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
1138                 BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1139 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL                       0
1140 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL                       (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1141 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v)          \
1142         (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
1143                 BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1144
1145 #define BP_ANADIG_ANA_MISC2_CONTROL3                            30
1146 #define BM_ANADIG_ANA_MISC2_CONTROL3                            (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
1147 #define BF_ANADIG_ANA_MISC2_CONTROL3(v)          \
1148         (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
1149                 BM_ANADIG_ANA_MISC2_CONTROL3)
1150 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME                      28
1151 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME                      (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1152 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v)          \
1153         (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
1154                 BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1155 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME                      26
1156 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME                      (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1157 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v)          \
1158         (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
1159                 BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1160 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME                      24
1161 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME                      (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1162 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v)          \
1163         (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
1164                 BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1165 #define BM_ANADIG_ANA_MISC2_CONTROL2                            (1 << 23)
1166 #define BM_ANADIG_ANA_MISC2_REG2_OK                             (1 << 22)
1167 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO                      (1 << 21)
1168 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS                      (1 << 19)
1169 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET                      16
1170 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET                      (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1171 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v)          \
1172         (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
1173                 BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1174 #define BM_ANADIG_ANA_MISC2_CONTROL1                            (1 << 15)
1175 #define BM_ANADIG_ANA_MISC2_REG1_OK                             (1 << 14)
1176 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO                      (1 << 13)
1177 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS                      (1 << 11)
1178 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET                      8
1179 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET                      (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
1180 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v)          \
1181         (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
1182                 BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
1183 #define BM_ANADIG_ANA_MISC2_CONTROL0                            (1 << 7)
1184 #define BM_ANADIG_ANA_MISC2_REG0_OK                             (1 << 6)
1185 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO                      (1 << 5)
1186 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS                      (1 << 3)
1187 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET                      0
1188 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET                      (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1189 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v)          \
1190         (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
1191                 BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1192
1193 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE                        20
1194 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE                        (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
1195 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v)          \
1196         (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
1197                 BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
1198 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE                         8
1199 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE                         (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
1200 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v)          \
1201         (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
1202                 BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
1203 #define BM_ANADIG_TEMPSENSE0_TEST                               (1 << 6)
1204 #define BP_ANADIG_TEMPSENSE0_VBGADJ                             3
1205 #define BM_ANADIG_TEMPSENSE0_VBGADJ                             (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
1206 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v)          \
1207         (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
1208                 BM_ANADIG_TEMPSENSE0_VBGADJ)
1209 #define BM_ANADIG_TEMPSENSE0_FINISHED                           (1 << 2)
1210 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP                       (1 << 1)
1211 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN                         (1 << 0)
1212
1213 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ                       0
1214 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ                       (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1215 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)          \
1216         (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
1217                 BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1218
1219
1220 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */