Merge branch 'master' of git://git.denx.de/u-boot-arm
[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h
1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9
10 #define ARCH_MXC
11
12 #define CONFIG_SYS_CACHELINE_SIZE       32
13
14 #define ROMCP_ARB_BASE_ADDR             0x00000000
15 #define ROMCP_ARB_END_ADDR              0x000FFFFF
16
17 #ifdef CONFIG_MX6SL
18 #define GPU_2D_ARB_BASE_ADDR            0x02200000
19 #define GPU_2D_ARB_END_ADDR             0x02203FFF
20 #define OPENVG_ARB_BASE_ADDR            0x02204000
21 #define OPENVG_ARB_END_ADDR             0x02207FFF
22 #elif CONFIG_MX6SX
23 #define CAAM_ARB_BASE_ADDR              0x00100000
24 #define CAAM_ARB_END_ADDR               0x00107FFF
25 #define GPU_ARB_BASE_ADDR               0x01800000
26 #define GPU_ARB_END_ADDR                0x01803FFF
27 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
28 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
29 #define M4_BOOTROM_BASE_ADDR                    0x007F8000
30
31 #define MXS_APBH_BASE                   APBH_DMA_ARB_BASE_ADDR
32 #define MXS_GPMI_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x02000)
33 #define MXS_BCH_BASE                    (APBH_DMA_ARB_BASE_ADDR + 0x04000)
34
35 #else
36 #define CAAM_ARB_BASE_ADDR              0x00100000
37 #define CAAM_ARB_END_ADDR               0x00103FFF
38 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
39 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
40 #define HDMI_ARB_BASE_ADDR              0x00120000
41 #define HDMI_ARB_END_ADDR               0x00128FFF
42 #define GPU_3D_ARB_BASE_ADDR            0x00130000
43 #define GPU_3D_ARB_END_ADDR             0x00133FFF
44 #define GPU_2D_ARB_BASE_ADDR            0x00134000
45 #define GPU_2D_ARB_END_ADDR             0x00137FFF
46 #define DTCP_ARB_BASE_ADDR              0x00138000
47 #define DTCP_ARB_END_ADDR               0x0013BFFF
48 #endif  /* CONFIG_MX6SL */
49
50 #define MXS_APBH_BASE                   APBH_DMA_ARB_BASE_ADDR
51 #define MXS_GPMI_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x02000)
52 #define MXS_BCH_BASE                    (APBH_DMA_ARB_BASE_ADDR + 0x04000)
53
54 /* GPV - PL301 configuration ports */
55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
56 #define GPV2_BASE_ADDR                  0x00D00000
57 #else
58 #define GPV2_BASE_ADDR                  0x00200000
59 #endif
60
61 #ifdef CONFIG_MX6SX
62 #define GPV3_BASE_ADDR                  0x00E00000
63 #define GPV4_BASE_ADDR                  0x00F00000
64 #define GPV5_BASE_ADDR                  0x01000000
65 #define GPV6_BASE_ADDR                  0x01100000
66 #define PCIE_ARB_BASE_ADDR              0x08000000
67 #define PCIE_ARB_END_ADDR               0x08FFFFFF
68
69 #else
70 #define GPV3_BASE_ADDR                  0x00300000
71 #define GPV4_BASE_ADDR                  0x00800000
72 #define PCIE_ARB_BASE_ADDR              0x01000000
73 #define PCIE_ARB_END_ADDR               0x01FFFFFF
74 #endif
75
76 #define IRAM_BASE_ADDR                  0x00900000
77 #define SCU_BASE_ADDR                   0x00A00000
78 #define IC_INTERFACES_BASE_ADDR         0x00A00100
79 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
80 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
81 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
82 #define L2_PL310_BASE                   0x00A02000
83 #define GPV0_BASE_ADDR                  0x00B00000
84 #define GPV1_BASE_ADDR                  0x00C00000
85
86 #define AIPS1_ARB_BASE_ADDR             0x02000000
87 #define AIPS1_ARB_END_ADDR              0x020FFFFF
88 #define AIPS2_ARB_BASE_ADDR             0x02100000
89 #define AIPS2_ARB_END_ADDR              0x021FFFFF
90 #ifdef CONFIG_MX6SX
91 #define AIPS3_BASE_ADDR                 0x02200000
92 #define AIPS3_END_ADDR                  0x022FFFFF
93 #define WEIM_ARB_BASE_ADDR              0x50000000
94 #define WEIM_ARB_END_ADDR               0x57FFFFFF
95 #define QSPI1_ARB_BASE_ADDR             0x60000000
96 #define QSPI1_ARB_END_ADDR              0x6FFFFFFF
97 #define QSPI2_ARB_BASE_ADDR             0x70000000
98 #define QSPI2_ARB_END_ADDR              0x7FFFFFFF
99 #else
100 #define SATA_ARB_BASE_ADDR              0x02200000
101 #define SATA_ARB_END_ADDR               0x02203FFF
102 #define OPENVG_ARB_BASE_ADDR            0x02204000
103 #define OPENVG_ARB_END_ADDR             0x02207FFF
104 #define HSI_ARB_BASE_ADDR               0x02208000
105 #define HSI_ARB_END_ADDR                0x0220BFFF
106 #define IPU1_ARB_BASE_ADDR              0x02400000
107 #define IPU1_ARB_END_ADDR               0x027FFFFF
108 #define IPU2_ARB_BASE_ADDR              0x02800000
109 #define IPU2_ARB_END_ADDR               0x02BFFFFF
110 #define WEIM_ARB_BASE_ADDR              0x08000000
111 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
112 #endif
113
114 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
115 #define MMDC0_ARB_BASE_ADDR             0x80000000
116 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
117 #define MMDC1_ARB_BASE_ADDR             0xC0000000
118 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
119 #else
120 #define MMDC0_ARB_BASE_ADDR             0x10000000
121 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
122 #define MMDC1_ARB_BASE_ADDR             0x80000000
123 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
124 #endif
125
126 #ifndef CONFIG_MX6SX
127 #define IPU_SOC_BASE_ADDR               IPU1_ARB_BASE_ADDR
128 #define IPU_SOC_OFFSET                  0x00200000
129 #endif
130
131 /* Defines for Blocks connected via AIPS (SkyBlue) */
132 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
133 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
134 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
135 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
136
137 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
138 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
139 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
140 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
141 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
142 #ifdef CONFIG_MX6SL
143 #define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
144 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
145 #define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
146 #define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
147 #define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
148 #define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
149 #define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
150 #define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
151 #else
152 #ifndef CONFIG_MX6SX
153 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
154 #endif
155 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
156 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
157 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
158 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
159 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
160 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
161 #endif
162
163 #ifndef CONFIG_MX6SX
164 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
165 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
166 #endif
167 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
168
169 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
170 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
171 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
172 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
173 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
174 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
175 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
176 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
177 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
178 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
179 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
180 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
181 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
182 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
183 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
184 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
185 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
186 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
187 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
188 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
189 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
190 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
191 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
192 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
193 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
194 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
195 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
196 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
197 #ifdef CONFIG_MX6SL
198 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
199 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
200 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
201 #elif CONFIG_MX6SX
202 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
203 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
204 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
205 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
206 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
207 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
208 #else
209 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
210 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
211 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
212 #endif
213
214 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
215 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
216 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
217 #define ARM_BASE_ADDR               (ATZ2_BASE_ADDR + 0x40000)
218 #ifdef CONFIG_MX6SL
219 #define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
220 #define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
221 #else
222 #define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
223 #define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
224 #endif
225
226 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
227 #ifdef CONFIG_MX6SL
228 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
229 #else
230 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
231 #endif
232
233 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
234 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
235 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
236 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
237 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
238 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
239 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
240 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
241 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
242 #ifdef CONFIG_MX6SL
243 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
244 #elif CONFIG_MX6SX
245 #define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
246 #else
247 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
248 #endif
249
250 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
251 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
252 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
253 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
254 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
255 #ifdef CONFIG_MX6SX
256 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
257 #else
258 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
259 #endif
260 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
261 #ifdef CONFIG_MX6SX
262 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
263 #else
264 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
265 #endif
266 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
267 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
268 #ifdef CONFIG_MX6SX
269 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
270 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
271 #define QSPI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
272 #else
273 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
274 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
275 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
276 #endif
277 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
278 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
279 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
280 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
281 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
282 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
283
284 #ifdef CONFIG_MX6SX
285 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
286 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
287 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
288 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
289 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
290 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
291 #define LCDIF1_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x20000)
292 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
293 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
294 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
295 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
296 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
297 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
298 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
299 #define WDOG3_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x88000)
300 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
301 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
302 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
303 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
304 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
305 #define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
306 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
307 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
308 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
309 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
310 #endif
311
312 #define CHIP_REV_1_0                 0x10
313 #define CHIP_REV_1_2                 0x12
314 #define CHIP_REV_1_5                 0x15
315 #ifndef CONFIG_MX6SX
316 #define IRAM_SIZE                    0x00040000
317 #else
318 #define IRAM_SIZE                    0x00020000
319 #endif
320 #define FEC_QUIRK_ENET_MAC
321
322 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
323 #include <asm/types.h>
324
325 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
326
327 /* System Reset Controller (SRC) */
328 struct src {
329         u32     scr;
330         u32     sbmr1;
331         u32     srsr;
332         u32     reserved1[2];
333         u32     sisr;
334         u32     simr;
335         u32     sbmr2;
336         u32     gpr1;
337         u32     gpr2;
338         u32     gpr3;
339         u32     gpr4;
340         u32     gpr5;
341         u32     gpr6;
342         u32     gpr7;
343         u32     gpr8;
344         u32     gpr9;
345         u32     gpr10;
346 };
347
348 /* GPR1 bitfields */
349 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET         21
350 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK           (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
351 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET           13
352 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK         (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
353
354 /* GPR3 bitfields */
355 #define IOMUXC_GPR3_GPU_DBG_OFFSET              29
356 #define IOMUXC_GPR3_GPU_DBG_MASK                (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
357 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET     28
358 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
359 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET     27
360 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
361 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET  26
362 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
363 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET  25
364 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
365 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET            21
366 #define IOMUXC_GPR3_OCRAM_CTL_MASK              (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
367 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET         17
368 #define IOMUXC_GPR3_OCRAM_STATUS_MASK           (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
369 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET     16
370 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
371 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET     15
372 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
373 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET     14
374 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
375 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET     13
376 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
377 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET     12
378 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
379 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET     11
380 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
381 #define IOMUXC_GPR3_IPU_DIAG_OFFSET             10
382 #define IOMUXC_GPR3_IPU_DIAG_MASK               (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
383
384 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0    0
385 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1    1
386 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0    2
387 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1    3
388
389 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET        8
390 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
391
392 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET        6
393 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
394
395 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET         4
396 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
397
398 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET         2
399 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
400
401
402 struct iomuxc {
403 #ifdef CONFIG_MX6SX
404         u8 reserved[0x4000];
405 #endif
406         u32 gpr[14];
407         u32 omux[5];
408         /* mux and pad registers */
409 };
410
411 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET            20
412 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK              (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
413 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET               16
414 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                 (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
415
416 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET                 15
417 #define IOMUXC_GPR2_BGREF_RRMODE_MASK                   (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
418 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES           (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
419 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES           (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
420 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH   0
421 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW    1
422
423 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET              10
424 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
425 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
426 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
427
428 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET              9
429 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
430 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
431 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
432
433 #define IOMUXC_GPR2_BITMAP_SPWG 0
434 #define IOMUXC_GPR2_BITMAP_JEIDA        1
435
436 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET              8
437 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
438 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
439 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
440
441 #define IOMUXC_GPR2_DATA_WIDTH_18       0
442 #define IOMUXC_GPR2_DATA_WIDTH_24       1
443
444 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET               7
445 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
446 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
447 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
448
449 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET              6
450 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
451 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
452 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
453
454 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET               5
455 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
456 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
457 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
458
459 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET                4
460 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                  (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
461
462 #define IOMUXC_GPR2_MODE_DISABLED       0
463 #define IOMUXC_GPR2_MODE_ENABLED_DI0    1
464 #define IOMUXC_GPR2_MODE_ENABLED_DI1    3
465
466 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET                2
467 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
468 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
469 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
470 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
471
472 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET                0
473 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
474 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
475 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
476 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
477
478 /* ECSPI registers */
479 struct cspi_regs {
480         u32 rxdata;
481         u32 txdata;
482         u32 ctrl;
483         u32 cfg;
484         u32 intr;
485         u32 dma;
486         u32 stat;
487         u32 period;
488 };
489
490 /*
491  * CSPI register definitions
492  */
493 #define MXC_ECSPI
494 #define MXC_CSPICTRL_EN         (1 << 0)
495 #define MXC_CSPICTRL_MODE       (1 << 1)
496 #define MXC_CSPICTRL_XCH        (1 << 2)
497 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
498 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
499 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
500 #define MXC_CSPICTRL_PREDIV(x)  (((x) & 0xF) << 12)
501 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
502 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
503 #define MXC_CSPICTRL_MAXBITS    0xfff
504 #define MXC_CSPICTRL_TC         (1 << 7)
505 #define MXC_CSPICTRL_RXOVF      (1 << 6)
506 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
507 #define MAX_SPI_BYTES   32
508 #define SPI_MAX_NUM     4
509
510 /* Bit position inside CTRL register to be associated with SS */
511 #define MXC_CSPICTRL_CHAN       18
512
513 /* Bit position inside CON register to be associated with SS */
514 #define MXC_CSPICON_PHA         0  /* SCLK phase control */
515 #define MXC_CSPICON_POL         4  /* SCLK polarity */
516 #define MXC_CSPICON_SSPOL       12 /* SS polarity */
517 #define MXC_CSPICON_CTL         20 /* inactive state of SCLK */
518 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
519 #define MXC_SPI_BASE_ADDRESSES \
520         ECSPI1_BASE_ADDR, \
521         ECSPI2_BASE_ADDR, \
522         ECSPI3_BASE_ADDR, \
523         ECSPI4_BASE_ADDR
524 #else
525 #define MXC_SPI_BASE_ADDRESSES \
526         ECSPI1_BASE_ADDR, \
527         ECSPI2_BASE_ADDR, \
528         ECSPI3_BASE_ADDR, \
529         ECSPI4_BASE_ADDR, \
530         ECSPI5_BASE_ADDR
531 #endif
532
533 struct ocotp_regs {
534         u32     ctrl;
535         u32     ctrl_set;
536         u32     ctrl_clr;
537         u32     ctrl_tog;
538         u32     timing;
539         u32     rsvd0[3];
540         u32     data;
541         u32     rsvd1[3];
542         u32     read_ctrl;
543         u32     rsvd2[3];
544         u32     read_fuse_data;
545         u32     rsvd3[3];
546         u32     sw_sticky;
547         u32     rsvd4[3];
548         u32     scs;
549         u32     scs_set;
550         u32     scs_clr;
551         u32     scs_tog;
552         u32     crc_addr;
553         u32     rsvd5[3];
554         u32     crc_value;
555         u32     rsvd6[3];
556         u32     version;
557         u32     rsvd7[0xdb];
558
559         struct fuse_bank {
560                 u32     fuse_regs[0x20];
561         } bank[16];
562 };
563
564 struct fuse_bank0_regs {
565         u32     lock;
566         u32     rsvd0[3];
567         u32     uid_low;
568         u32     rsvd1[3];
569         u32     uid_high;
570         u32     rsvd2[3];
571         u32     rsvd3[4];
572         u32     rsvd4[4];
573         u32     rsvd5[4];
574         u32     cfg5;
575         u32     rsvd6[3];
576         u32     rsvd7[4];
577 };
578
579 #ifdef CONFIG_MX6SX
580 struct fuse_bank4_regs {
581         u32 sjc_resp_low;
582         u32 rsvd0[3];
583         u32 sjc_resp_high;
584         u32 rsvd1[3];
585         u32 mac_addr_low;
586         u32 rsvd2[3];
587         u32 mac_addr_high;
588         u32 rsvd3[3];
589         u32 mac_addr2;
590         u32 rsvd4[7];
591         u32 gp1;
592         u32 rsvd5[7];
593 };
594 #else
595 struct fuse_bank4_regs {
596         u32     sjc_resp_low;
597         u32     rsvd0[3];
598         u32     sjc_resp_high;
599         u32     rsvd1[3];
600         u32     mac_addr_low;
601         u32     rsvd2[3];
602         u32     mac_addr_high;
603         u32     rsvd3[0xb];
604         u32     gp1;
605         u32     rsvd4[3];
606         u32     gp2;
607         u32     rsvd5[3];
608 };
609 #endif
610
611 struct aipstz_regs {
612         u32     mprot0;
613         u32     mprot1;
614         u32     rsvd[0xe];
615         u32     opacr0;
616         u32     opacr1;
617         u32     opacr2;
618         u32     opacr3;
619         u32     opacr4;
620 };
621
622 struct anatop_regs {
623         u32     pll_sys;                /* 0x000 */
624         u32     pll_sys_set;            /* 0x004 */
625         u32     pll_sys_clr;            /* 0x008 */
626         u32     pll_sys_tog;            /* 0x00c */
627         u32     usb1_pll_480_ctrl;      /* 0x010 */
628         u32     usb1_pll_480_ctrl_set;  /* 0x014 */
629         u32     usb1_pll_480_ctrl_clr;  /* 0x018 */
630         u32     usb1_pll_480_ctrl_tog;  /* 0x01c */
631         u32     usb2_pll_480_ctrl;      /* 0x020 */
632         u32     usb2_pll_480_ctrl_set;  /* 0x024 */
633         u32     usb2_pll_480_ctrl_clr;  /* 0x028 */
634         u32     usb2_pll_480_ctrl_tog;  /* 0x02c */
635         u32     pll_528;                /* 0x030 */
636         u32     pll_528_set;            /* 0x034 */
637         u32     pll_528_clr;            /* 0x038 */
638         u32     pll_528_tog;            /* 0x03c */
639         u32     pll_528_ss;             /* 0x040 */
640         u32     rsvd0[3];
641         u32     pll_528_num;            /* 0x050 */
642         u32     rsvd1[3];
643         u32     pll_528_denom;          /* 0x060 */
644         u32     rsvd2[3];
645         u32     pll_audio;              /* 0x070 */
646         u32     pll_audio_set;          /* 0x074 */
647         u32     pll_audio_clr;          /* 0x078 */
648         u32     pll_audio_tog;          /* 0x07c */
649         u32     pll_audio_num;          /* 0x080 */
650         u32     rsvd3[3];
651         u32     pll_audio_denom;        /* 0x090 */
652         u32     rsvd4[3];
653         u32     pll_video;              /* 0x0a0 */
654         u32     pll_video_set;          /* 0x0a4 */
655         u32     pll_video_clr;          /* 0x0a8 */
656         u32     pll_video_tog;          /* 0x0ac */
657         u32     pll_video_num;          /* 0x0b0 */
658         u32     rsvd5[3];
659         u32     pll_video_denom;        /* 0x0c0 */
660         u32     rsvd6[3];
661         u32     pll_mlb;                /* 0x0d0 */
662         u32     pll_mlb_set;            /* 0x0d4 */
663         u32     pll_mlb_clr;            /* 0x0d8 */
664         u32     pll_mlb_tog;            /* 0x0dc */
665         u32     pll_enet;               /* 0x0e0 */
666         u32     pll_enet_set;           /* 0x0e4 */
667         u32     pll_enet_clr;           /* 0x0e8 */
668         u32     pll_enet_tog;           /* 0x0ec */
669         u32     pfd_480;                /* 0x0f0 */
670         u32     pfd_480_set;            /* 0x0f4 */
671         u32     pfd_480_clr;            /* 0x0f8 */
672         u32     pfd_480_tog;            /* 0x0fc */
673         u32     pfd_528;                /* 0x100 */
674         u32     pfd_528_set;            /* 0x104 */
675         u32     pfd_528_clr;            /* 0x108 */
676         u32     pfd_528_tog;            /* 0x10c */
677         u32     reg_1p1;                /* 0x110 */
678         u32     reg_1p1_set;            /* 0x114 */
679         u32     reg_1p1_clr;            /* 0x118 */
680         u32     reg_1p1_tog;            /* 0x11c */
681         u32     reg_3p0;                /* 0x120 */
682         u32     reg_3p0_set;            /* 0x124 */
683         u32     reg_3p0_clr;            /* 0x128 */
684         u32     reg_3p0_tog;            /* 0x12c */
685         u32     reg_2p5;                /* 0x130 */
686         u32     reg_2p5_set;            /* 0x134 */
687         u32     reg_2p5_clr;            /* 0x138 */
688         u32     reg_2p5_tog;            /* 0x13c */
689         u32     reg_core;               /* 0x140 */
690         u32     reg_core_set;           /* 0x144 */
691         u32     reg_core_clr;           /* 0x148 */
692         u32     reg_core_tog;           /* 0x14c */
693         u32     ana_misc0;              /* 0x150 */
694         u32     ana_misc0_set;          /* 0x154 */
695         u32     ana_misc0_clr;          /* 0x158 */
696         u32     ana_misc0_tog;          /* 0x15c */
697         u32     ana_misc1;              /* 0x160 */
698         u32     ana_misc1_set;          /* 0x164 */
699         u32     ana_misc1_clr;          /* 0x168 */
700         u32     ana_misc1_tog;          /* 0x16c */
701         u32     ana_misc2;              /* 0x170 */
702         u32     ana_misc2_set;          /* 0x174 */
703         u32     ana_misc2_clr;          /* 0x178 */
704         u32     ana_misc2_tog;          /* 0x17c */
705         u32     tempsense0;             /* 0x180 */
706         u32     tempsense0_set;         /* 0x184 */
707         u32     tempsense0_clr;         /* 0x188 */
708         u32     tempsense0_tog;         /* 0x18c */
709         u32     tempsense1;             /* 0x190 */
710         u32     tempsense1_set;         /* 0x194 */
711         u32     tempsense1_clr;         /* 0x198 */
712         u32     tempsense1_tog;         /* 0x19c */
713         u32     usb1_vbus_detect;       /* 0x1a0 */
714         u32     usb1_vbus_detect_set;   /* 0x1a4 */
715         u32     usb1_vbus_detect_clr;   /* 0x1a8 */
716         u32     usb1_vbus_detect_tog;   /* 0x1ac */
717         u32     usb1_chrg_detect;       /* 0x1b0 */
718         u32     usb1_chrg_detect_set;   /* 0x1b4 */
719         u32     usb1_chrg_detect_clr;   /* 0x1b8 */
720         u32     usb1_chrg_detect_tog;   /* 0x1bc */
721         u32     usb1_vbus_det_stat;     /* 0x1c0 */
722         u32     usb1_vbus_det_stat_set; /* 0x1c4 */
723         u32     usb1_vbus_det_stat_clr; /* 0x1c8 */
724         u32     usb1_vbus_det_stat_tog; /* 0x1cc */
725         u32     usb1_chrg_det_stat;     /* 0x1d0 */
726         u32     usb1_chrg_det_stat_set; /* 0x1d4 */
727         u32     usb1_chrg_det_stat_clr; /* 0x1d8 */
728         u32     usb1_chrg_det_stat_tog; /* 0x1dc */
729         u32     usb1_loopback;          /* 0x1e0 */
730         u32     usb1_loopback_set;      /* 0x1e4 */
731         u32     usb1_loopback_clr;      /* 0x1e8 */
732         u32     usb1_loopback_tog;      /* 0x1ec */
733         u32     usb1_misc;              /* 0x1f0 */
734         u32     usb1_misc_set;          /* 0x1f4 */
735         u32     usb1_misc_clr;          /* 0x1f8 */
736         u32     usb1_misc_tog;          /* 0x1fc */
737         u32     usb2_vbus_detect;       /* 0x200 */
738         u32     usb2_vbus_detect_set;   /* 0x204 */
739         u32     usb2_vbus_detect_clr;   /* 0x208 */
740         u32     usb2_vbus_detect_tog;   /* 0x20c */
741         u32     usb2_chrg_detect;       /* 0x210 */
742         u32     usb2_chrg_detect_set;   /* 0x214 */
743         u32     usb2_chrg_detect_clr;   /* 0x218 */
744         u32     usb2_chrg_detect_tog;   /* 0x21c */
745         u32     usb2_vbus_det_stat;     /* 0x220 */
746         u32     usb2_vbus_det_stat_set; /* 0x224 */
747         u32     usb2_vbus_det_stat_clr; /* 0x228 */
748         u32     usb2_vbus_det_stat_tog; /* 0x22c */
749         u32     usb2_chrg_det_stat;     /* 0x230 */
750         u32     usb2_chrg_det_stat_set; /* 0x234 */
751         u32     usb2_chrg_det_stat_clr; /* 0x238 */
752         u32     usb2_chrg_det_stat_tog; /* 0x23c */
753         u32     usb2_loopback;          /* 0x240 */
754         u32     usb2_loopback_set;      /* 0x244 */
755         u32     usb2_loopback_clr;      /* 0x248 */
756         u32     usb2_loopback_tog;      /* 0x24c */
757         u32     usb2_misc;              /* 0x250 */
758         u32     usb2_misc_set;          /* 0x254 */
759         u32     usb2_misc_clr;          /* 0x258 */
760         u32     usb2_misc_tog;          /* 0x25c */
761         u32     digprog;                /* 0x260 */
762         u32     reserved1[7];
763         u32     digprog_sololite;       /* 0x280 */
764 };
765
766 #define ANATOP_PFD_FRAC_SHIFT(n)        ((n)*8)
767 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
768 #define ANATOP_PFD_STABLE_SHIFT(n)      (6+((n)*8))
769 #define ANATOP_PFD_STABLE_MASK(n)       (1<<ANATOP_PFD_STABLE_SHIFT(n))
770 #define ANATOP_PFD_CLKGATE_SHIFT(n)     (7+((n)*8))
771 #define ANATOP_PFD_CLKGATE_MASK(n)      (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
772
773 struct wdog_regs {
774         u16     wcr;    /* Control */
775         u16     wsr;    /* Service */
776         u16     wrsr;   /* Reset Status */
777         u16     wicr;   /* Interrupt Control */
778         u16     wmcr;   /* Miscellaneous Control */
779 };
780
781 #define PWMCR_PRESCALER(x)      (((x - 1) & 0xFFF) << 4)
782 #define PWMCR_DOZEEN            (1 << 24)
783 #define PWMCR_WAITEN            (1 << 23)
784 #define PWMCR_DBGEN             (1 << 22)
785 #define PWMCR_CLKSRC_IPG_HIGH   (2 << 16)
786 #define PWMCR_CLKSRC_IPG        (1 << 16)
787 #define PWMCR_EN                (1 << 0)
788
789 struct pwm_regs {
790         u32     cr;
791         u32     sr;
792         u32     ir;
793         u32     sar;
794         u32     pr;
795         u32     cnr;
796 };
797 #endif /* __ASSEMBLER__*/
798 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */