7ef7152678702a1318b6f7eee45143c8fe22f357
[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h
1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9
10 #define ARCH_MXC
11
12 #define CONFIG_SYS_CACHELINE_SIZE       32
13
14 #define ROMCP_ARB_BASE_ADDR             0x00000000
15 #define ROMCP_ARB_END_ADDR              0x000FFFFF
16
17 #ifdef CONFIG_MX6SL
18 #define GPU_2D_ARB_BASE_ADDR            0x02200000
19 #define GPU_2D_ARB_END_ADDR             0x02203FFF
20 #define OPENVG_ARB_BASE_ADDR            0x02204000
21 #define OPENVG_ARB_END_ADDR             0x02207FFF
22 #else
23 #define CAAM_ARB_BASE_ADDR              0x00100000
24 #define CAAM_ARB_END_ADDR               0x00103FFF
25 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
26 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
27 #define HDMI_ARB_BASE_ADDR              0x00120000
28 #define HDMI_ARB_END_ADDR               0x00128FFF
29 #define GPU_3D_ARB_BASE_ADDR            0x00130000
30 #define GPU_3D_ARB_END_ADDR             0x00133FFF
31 #define GPU_2D_ARB_BASE_ADDR            0x00134000
32 #define GPU_2D_ARB_END_ADDR             0x00137FFF
33 #define DTCP_ARB_BASE_ADDR              0x00138000
34 #define DTCP_ARB_END_ADDR               0x0013BFFF
35 #endif  /* CONFIG_MX6SL */
36
37 #define MXS_APBH_BASE                   APBH_DMA_ARB_BASE_ADDR
38 #define MXS_GPMI_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x02000)
39 #define MXS_BCH_BASE                    (APBH_DMA_ARB_BASE_ADDR + 0x04000)
40
41 /* GPV - PL301 configuration ports */
42 #ifdef CONFIG_MX6SL
43 #define GPV2_BASE_ADDR                  0x00D00000
44 #else
45 #define GPV2_BASE_ADDR                  0x00200000
46 #endif
47
48 #define GPV3_BASE_ADDR                  0x00300000
49 #define GPV4_BASE_ADDR                  0x00800000
50 #define IRAM_BASE_ADDR                  0x00900000
51 #define SCU_BASE_ADDR                   0x00A00000
52 #define IC_INTERFACES_BASE_ADDR         0x00A00100
53 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
54 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
55 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
56 #define GPV0_BASE_ADDR                  0x00B00000
57 #define GPV1_BASE_ADDR                  0x00C00000
58 #define PCIE_ARB_BASE_ADDR              0x01000000
59 #define PCIE_ARB_END_ADDR               0x01FFFFFF
60
61 #define AIPS1_ARB_BASE_ADDR             0x02000000
62 #define AIPS1_ARB_END_ADDR              0x020FFFFF
63 #define AIPS2_ARB_BASE_ADDR             0x02100000
64 #define AIPS2_ARB_END_ADDR              0x021FFFFF
65 #define SATA_ARB_BASE_ADDR              0x02200000
66 #define SATA_ARB_END_ADDR               0x02203FFF
67 #define OPENVG_ARB_BASE_ADDR            0x02204000
68 #define OPENVG_ARB_END_ADDR             0x02207FFF
69 #define HSI_ARB_BASE_ADDR               0x02208000
70 #define HSI_ARB_END_ADDR                0x0220BFFF
71 #define IPU1_ARB_BASE_ADDR              0x02400000
72 #define IPU1_ARB_END_ADDR               0x027FFFFF
73 #define IPU2_ARB_BASE_ADDR              0x02800000
74 #define IPU2_ARB_END_ADDR               0x02BFFFFF
75 #define WEIM_ARB_BASE_ADDR              0x08000000
76 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
77
78 #ifdef CONFIG_MX6SL
79 #define MMDC0_ARB_BASE_ADDR             0x80000000
80 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
81 #define MMDC1_ARB_BASE_ADDR             0xC0000000
82 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
83 #else
84 #define MMDC0_ARB_BASE_ADDR             0x10000000
85 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
86 #define MMDC1_ARB_BASE_ADDR             0x80000000
87 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
88 #endif
89
90 #define IPU_SOC_BASE_ADDR               IPU1_ARB_BASE_ADDR
91 #define IPU_SOC_OFFSET                  0x00200000
92
93 /* Defines for Blocks connected via AIPS (SkyBlue) */
94 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
95 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
96 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
97 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
98
99 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
100 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
101 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
102 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
103 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
104 #ifdef CONFIG_MX6SL
105 #define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
106 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
107 #define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
108 #define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
109 #define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
110 #define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
111 #define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
112 #define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
113 #else
114 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
115 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
116 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
117 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
118 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
119 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
120 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
121 #endif
122
123 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
124 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
125 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
126
127 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
128 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
129 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
130 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
131 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
132 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
133 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
134 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
135 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
136 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
137 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
138 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
139 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
140 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
141 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
142 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
143 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
144 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
145 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
146 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
147 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
148 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
149 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
150 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
151 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
152 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
153 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
154 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
155 #ifdef CONFIG_MX6SL
156 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
157 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
158 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
159 #else
160 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
161 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
162 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
163 #endif
164
165 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
166 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
167 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
168 #define ARM_BASE_ADDR               (ATZ2_BASE_ADDR + 0x40000)
169 #ifdef CONFIG_MX6SL
170 #define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
171 #define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
172 #else
173 #define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
174 #define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
175 #endif
176
177 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
178 #ifdef CONFIG_MX6SL
179 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
180 #else
181 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
182 #endif
183
184 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
185 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
186 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
187 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
188 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
189 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
190 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
191 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
192 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
193 #ifdef CONFIG_MX6SL
194 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
195 #else
196 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
197 #endif
198
199 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
200 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
201 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
202 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
203 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
204 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
205 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
206 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
207 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
208 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
209 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
210 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
211 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
212 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
213 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
214 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
215 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
216 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
217
218 #define CHIP_REV_1_0                 0x10
219 #define IRAM_SIZE                    0x00040000
220 #define FEC_QUIRK_ENET_MAC
221
222 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
223 #include <asm/types.h>
224
225 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
226
227 /* System Reset Controller (SRC) */
228 struct src {
229         u32     scr;
230         u32     sbmr1;
231         u32     srsr;
232         u32     reserved1[2];
233         u32     sisr;
234         u32     simr;
235         u32     sbmr2;
236         u32     gpr1;
237         u32     gpr2;
238         u32     gpr3;
239         u32     gpr4;
240         u32     gpr5;
241         u32     gpr6;
242         u32     gpr7;
243         u32     gpr8;
244         u32     gpr9;
245         u32     gpr10;
246 };
247
248 /* GPR3 bitfields */
249 #define IOMUXC_GPR3_GPU_DBG_OFFSET              29
250 #define IOMUXC_GPR3_GPU_DBG_MASK                (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
251 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET     28
252 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
253 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET     27
254 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
255 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET  26
256 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
257 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET  25
258 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
259 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET            21
260 #define IOMUXC_GPR3_OCRAM_CTL_MASK              (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
261 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET         17
262 #define IOMUXC_GPR3_OCRAM_STATUS_MASK           (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
263 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET     16
264 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
265 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET     15
266 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
267 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET     14
268 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
269 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET     13
270 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
271 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET     12
272 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
273 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET     11
274 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
275 #define IOMUXC_GPR3_IPU_DIAG_OFFSET             10
276 #define IOMUXC_GPR3_IPU_DIAG_MASK               (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
277
278 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0    0
279 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1    1
280 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0    2
281 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1    3
282
283 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET        8
284 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
285
286 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET        6
287 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
288
289 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET         4
290 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
291
292 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET         2
293 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
294
295
296 struct iomuxc {
297         u32 gpr[14];
298         u32 omux[5];
299         /* mux and pad registers */
300 };
301
302 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET            20
303 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK              (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
304 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET               16
305 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                 (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
306
307 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET                 15
308 #define IOMUXC_GPR2_BGREF_RRMODE_MASK                   (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
309 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES           (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
310 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES           (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
311 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH   0
312 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW    1
313
314 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET              10
315 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
316 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
317 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
318
319 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET              9
320 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
321 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
322 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
323
324 #define IOMUXC_GPR2_BITMAP_SPWG 0
325 #define IOMUXC_GPR2_BITMAP_JEIDA        1
326
327 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET              8
328 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
329 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
330 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
331
332 #define IOMUXC_GPR2_DATA_WIDTH_18       0
333 #define IOMUXC_GPR2_DATA_WIDTH_24       1
334
335 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET               7
336 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
337 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
338 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
339
340 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET              6
341 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
342 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
343 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
344
345 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET               5
346 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
347 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
348 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
349
350 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET                4
351 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                  (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
352
353 #define IOMUXC_GPR2_MODE_DISABLED       0
354 #define IOMUXC_GPR2_MODE_ENABLED_DI0    1
355 #define IOMUXC_GPR2_MODE_ENABLED_DI1    3
356
357 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET                2
358 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
359 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
360 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
361 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
362
363 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET                0
364 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
365 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
366 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
367 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
368
369 /* ECSPI registers */
370 struct cspi_regs {
371         u32 rxdata;
372         u32 txdata;
373         u32 ctrl;
374         u32 cfg;
375         u32 intr;
376         u32 dma;
377         u32 stat;
378         u32 period;
379 };
380
381 /*
382  * CSPI register definitions
383  */
384 #define MXC_ECSPI
385 #define MXC_CSPICTRL_EN         (1 << 0)
386 #define MXC_CSPICTRL_MODE       (1 << 1)
387 #define MXC_CSPICTRL_XCH        (1 << 2)
388 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
389 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
390 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
391 #define MXC_CSPICTRL_PREDIV(x)  (((x) & 0xF) << 12)
392 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
393 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
394 #define MXC_CSPICTRL_MAXBITS    0xfff
395 #define MXC_CSPICTRL_TC         (1 << 7)
396 #define MXC_CSPICTRL_RXOVF      (1 << 6)
397 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
398 #define MAX_SPI_BYTES   32
399
400 /* Bit position inside CTRL register to be associated with SS */
401 #define MXC_CSPICTRL_CHAN       18
402
403 /* Bit position inside CON register to be associated with SS */
404 #define MXC_CSPICON_POL         4
405 #define MXC_CSPICON_PHA         0
406 #define MXC_CSPICON_SSPOL       12
407 #ifdef CONFIG_MX6SL
408 #define MXC_SPI_BASE_ADDRESSES \
409         ECSPI1_BASE_ADDR, \
410         ECSPI2_BASE_ADDR, \
411         ECSPI3_BASE_ADDR, \
412         ECSPI4_BASE_ADDR
413 #else
414 #define MXC_SPI_BASE_ADDRESSES \
415         ECSPI1_BASE_ADDR, \
416         ECSPI2_BASE_ADDR, \
417         ECSPI3_BASE_ADDR, \
418         ECSPI4_BASE_ADDR, \
419         ECSPI5_BASE_ADDR
420 #endif
421
422 struct ocotp_regs {
423         u32     ctrl;
424         u32     ctrl_set;
425         u32     ctrl_clr;
426         u32     ctrl_tog;
427         u32     timing;
428         u32     rsvd0[3];
429         u32     data;
430         u32     rsvd1[3];
431         u32     read_ctrl;
432         u32     rsvd2[3];
433         u32     read_fuse_data;
434         u32     rsvd3[3];
435         u32     sw_sticky;
436         u32     rsvd4[3];
437         u32     scs;
438         u32     scs_set;
439         u32     scs_clr;
440         u32     scs_tog;
441         u32     crc_addr;
442         u32     rsvd5[3];
443         u32     crc_value;
444         u32     rsvd6[3];
445         u32     version;
446         u32     rsvd7[0xdb];
447
448         struct fuse_bank {
449                 u32     fuse_regs[0x20];
450         } bank[16];
451 };
452
453 struct fuse_bank0_regs {
454         u32     lock;
455         u32     rsvd0[3];
456         u32     uid_low;
457         u32     rsvd1[3];
458         u32     uid_high;
459         u32     rsvd2[3];
460         u32     rsvd3[4];
461         u32     rsvd4[4];
462         u32     rsvd5[4];
463         u32     cfg5;
464         u32     rsvd6[3];
465         u32     rsvd7[4];
466 };
467
468 struct fuse_bank4_regs {
469         u32     sjc_resp_low;
470         u32     rsvd0[3];
471         u32     sjc_resp_high;
472         u32     rsvd1[3];
473         u32     mac_addr_low;
474         u32     rsvd2[3];
475         u32     mac_addr_high;
476         u32     rsvd3[0xb];
477         u32     gp1;
478         u32     rsvd4[3];
479         u32     gp2;
480         u32     rsvd5[3];
481 };
482
483 struct aipstz_regs {
484         u32     mprot0;
485         u32     mprot1;
486         u32     rsvd[0xe];
487         u32     opacr0;
488         u32     opacr1;
489         u32     opacr2;
490         u32     opacr3;
491         u32     opacr4;
492 };
493
494 struct anatop_regs {
495         u32     pll_sys;                /* 0x000 */
496         u32     pll_sys_set;            /* 0x004 */
497         u32     pll_sys_clr;            /* 0x008 */
498         u32     pll_sys_tog;            /* 0x00c */
499         u32     usb1_pll_480_ctrl;      /* 0x010 */
500         u32     usb1_pll_480_ctrl_set;  /* 0x014 */
501         u32     usb1_pll_480_ctrl_clr;  /* 0x018 */
502         u32     usb1_pll_480_ctrl_tog;  /* 0x01c */
503         u32     usb2_pll_480_ctrl;      /* 0x020 */
504         u32     usb2_pll_480_ctrl_set;  /* 0x024 */
505         u32     usb2_pll_480_ctrl_clr;  /* 0x028 */
506         u32     usb2_pll_480_ctrl_tog;  /* 0x02c */
507         u32     pll_528;                /* 0x030 */
508         u32     pll_528_set;            /* 0x034 */
509         u32     pll_528_clr;            /* 0x038 */
510         u32     pll_528_tog;            /* 0x03c */
511         u32     pll_528_ss;             /* 0x040 */
512         u32     rsvd0[3];
513         u32     pll_528_num;            /* 0x050 */
514         u32     rsvd1[3];
515         u32     pll_528_denom;          /* 0x060 */
516         u32     rsvd2[3];
517         u32     pll_audio;              /* 0x070 */
518         u32     pll_audio_set;          /* 0x074 */
519         u32     pll_audio_clr;          /* 0x078 */
520         u32     pll_audio_tog;          /* 0x07c */
521         u32     pll_audio_num;          /* 0x080 */
522         u32     rsvd3[3];
523         u32     pll_audio_denom;        /* 0x090 */
524         u32     rsvd4[3];
525         u32     pll_video;              /* 0x0a0 */
526         u32     pll_video_set;          /* 0x0a4 */
527         u32     pll_video_clr;          /* 0x0a8 */
528         u32     pll_video_tog;          /* 0x0ac */
529         u32     pll_video_num;          /* 0x0b0 */
530         u32     rsvd5[3];
531         u32     pll_video_denom;        /* 0x0c0 */
532         u32     rsvd6[3];
533         u32     pll_mlb;                /* 0x0d0 */
534         u32     pll_mlb_set;            /* 0x0d4 */
535         u32     pll_mlb_clr;            /* 0x0d8 */
536         u32     pll_mlb_tog;            /* 0x0dc */
537         u32     pll_enet;               /* 0x0e0 */
538         u32     pll_enet_set;           /* 0x0e4 */
539         u32     pll_enet_clr;           /* 0x0e8 */
540         u32     pll_enet_tog;           /* 0x0ec */
541         u32     pfd_480;                /* 0x0f0 */
542         u32     pfd_480_set;            /* 0x0f4 */
543         u32     pfd_480_clr;            /* 0x0f8 */
544         u32     pfd_480_tog;            /* 0x0fc */
545         u32     pfd_528;                /* 0x100 */
546         u32     pfd_528_set;            /* 0x104 */
547         u32     pfd_528_clr;            /* 0x108 */
548         u32     pfd_528_tog;            /* 0x10c */
549         u32     reg_1p1;                /* 0x110 */
550         u32     reg_1p1_set;            /* 0x114 */
551         u32     reg_1p1_clr;            /* 0x118 */
552         u32     reg_1p1_tog;            /* 0x11c */
553         u32     reg_3p0;                /* 0x120 */
554         u32     reg_3p0_set;            /* 0x124 */
555         u32     reg_3p0_clr;            /* 0x128 */
556         u32     reg_3p0_tog;            /* 0x12c */
557         u32     reg_2p5;                /* 0x130 */
558         u32     reg_2p5_set;            /* 0x134 */
559         u32     reg_2p5_clr;            /* 0x138 */
560         u32     reg_2p5_tog;            /* 0x13c */
561         u32     reg_core;               /* 0x140 */
562         u32     reg_core_set;           /* 0x144 */
563         u32     reg_core_clr;           /* 0x148 */
564         u32     reg_core_tog;           /* 0x14c */
565         u32     ana_misc0;              /* 0x150 */
566         u32     ana_misc0_set;          /* 0x154 */
567         u32     ana_misc0_clr;          /* 0x158 */
568         u32     ana_misc0_tog;          /* 0x15c */
569         u32     ana_misc1;              /* 0x160 */
570         u32     ana_misc1_set;          /* 0x164 */
571         u32     ana_misc1_clr;          /* 0x168 */
572         u32     ana_misc1_tog;          /* 0x16c */
573         u32     ana_misc2;              /* 0x170 */
574         u32     ana_misc2_set;          /* 0x174 */
575         u32     ana_misc2_clr;          /* 0x178 */
576         u32     ana_misc2_tog;          /* 0x17c */
577         u32     tempsense0;             /* 0x180 */
578         u32     tempsense0_set;         /* 0x184 */
579         u32     tempsense0_clr;         /* 0x188 */
580         u32     tempsense0_tog;         /* 0x18c */
581         u32     tempsense1;             /* 0x190 */
582         u32     tempsense1_set;         /* 0x194 */
583         u32     tempsense1_clr;         /* 0x198 */
584         u32     tempsense1_tog;         /* 0x19c */
585         u32     usb1_vbus_detect;       /* 0x1a0 */
586         u32     usb1_vbus_detect_set;   /* 0x1a4 */
587         u32     usb1_vbus_detect_clr;   /* 0x1a8 */
588         u32     usb1_vbus_detect_tog;   /* 0x1ac */
589         u32     usb1_chrg_detect;       /* 0x1b0 */
590         u32     usb1_chrg_detect_set;   /* 0x1b4 */
591         u32     usb1_chrg_detect_clr;   /* 0x1b8 */
592         u32     usb1_chrg_detect_tog;   /* 0x1bc */
593         u32     usb1_vbus_det_stat;     /* 0x1c0 */
594         u32     usb1_vbus_det_stat_set; /* 0x1c4 */
595         u32     usb1_vbus_det_stat_clr; /* 0x1c8 */
596         u32     usb1_vbus_det_stat_tog; /* 0x1cc */
597         u32     usb1_chrg_det_stat;     /* 0x1d0 */
598         u32     usb1_chrg_det_stat_set; /* 0x1d4 */
599         u32     usb1_chrg_det_stat_clr; /* 0x1d8 */
600         u32     usb1_chrg_det_stat_tog; /* 0x1dc */
601         u32     usb1_loopback;          /* 0x1e0 */
602         u32     usb1_loopback_set;      /* 0x1e4 */
603         u32     usb1_loopback_clr;      /* 0x1e8 */
604         u32     usb1_loopback_tog;      /* 0x1ec */
605         u32     usb1_misc;              /* 0x1f0 */
606         u32     usb1_misc_set;          /* 0x1f4 */
607         u32     usb1_misc_clr;          /* 0x1f8 */
608         u32     usb1_misc_tog;          /* 0x1fc */
609         u32     usb2_vbus_detect;       /* 0x200 */
610         u32     usb2_vbus_detect_set;   /* 0x204 */
611         u32     usb2_vbus_detect_clr;   /* 0x208 */
612         u32     usb2_vbus_detect_tog;   /* 0x20c */
613         u32     usb2_chrg_detect;       /* 0x210 */
614         u32     usb2_chrg_detect_set;   /* 0x214 */
615         u32     usb2_chrg_detect_clr;   /* 0x218 */
616         u32     usb2_chrg_detect_tog;   /* 0x21c */
617         u32     usb2_vbus_det_stat;     /* 0x220 */
618         u32     usb2_vbus_det_stat_set; /* 0x224 */
619         u32     usb2_vbus_det_stat_clr; /* 0x228 */
620         u32     usb2_vbus_det_stat_tog; /* 0x22c */
621         u32     usb2_chrg_det_stat;     /* 0x230 */
622         u32     usb2_chrg_det_stat_set; /* 0x234 */
623         u32     usb2_chrg_det_stat_clr; /* 0x238 */
624         u32     usb2_chrg_det_stat_tog; /* 0x23c */
625         u32     usb2_loopback;          /* 0x240 */
626         u32     usb2_loopback_set;      /* 0x244 */
627         u32     usb2_loopback_clr;      /* 0x248 */
628         u32     usb2_loopback_tog;      /* 0x24c */
629         u32     usb2_misc;              /* 0x250 */
630         u32     usb2_misc_set;          /* 0x254 */
631         u32     usb2_misc_clr;          /* 0x258 */
632         u32     usb2_misc_tog;          /* 0x25c */
633         u32     digprog;                /* 0x260 */
634         u32     reserved1[7];
635         u32     digprog_sololite;       /* 0x280 */
636 };
637
638 #define ANATOP_PFD_FRAC_SHIFT(n)        ((n)*8)
639 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
640 #define ANATOP_PFD_STABLE_SHIFT(n)      (6+((n)*8))
641 #define ANATOP_PFD_STABLE_MASK(n)       (1<<ANATOP_PFD_STABLE_SHIFT(n))
642 #define ANATOP_PFD_CLKGATE_SHIFT(n)     (7+((n)*8))
643 #define ANATOP_PFD_CLKGATE_MASK(n)      (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
644
645 struct iomuxc_base_regs {
646         u32     gpr[14];        /* 0x000 */
647         u32     obsrv[5];       /* 0x038 */
648         u32     swmux_ctl[197]; /* 0x04c */
649         u32     swpad_ctl[250]; /* 0x360 */
650         u32     swgrp[26];      /* 0x748 */
651         u32     daisy[104];     /* 0x7b0..94c */
652 };
653
654 struct wdog_regs {
655         u16     wcr;    /* Control */
656         u16     wsr;    /* Service */
657         u16     wrsr;   /* Reset Status */
658         u16     wicr;   /* Interrupt Control */
659         u16     wmcr;   /* Miscellaneous Control */
660 };
661
662 #endif /* __ASSEMBLER__*/
663 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */