2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
10 #include <asm/imx-common/regs-common.h>
15 #define CONFIG_SYS_CACHELINE_SIZE 64
17 #define CONFIG_SYS_CACHELINE_SIZE 32
20 #define ROMCP_ARB_BASE_ADDR 0x00000000
21 #define ROMCP_ARB_END_ADDR 0x000FFFFF
23 #ifdef CONFIG_SOC_MX6SL
24 #define GPU_2D_ARB_BASE_ADDR 0x02200000
25 #define GPU_2D_ARB_END_ADDR 0x02203FFF
26 #define OPENVG_ARB_BASE_ADDR 0x02204000
27 #define OPENVG_ARB_END_ADDR 0x02207FFF
28 #elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
29 #define CAAM_ARB_BASE_ADDR 0x00100000
30 #define CAAM_ARB_END_ADDR 0x00107FFF
31 #define GPU_ARB_BASE_ADDR 0x01800000
32 #define GPU_ARB_END_ADDR 0x01803FFF
33 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
34 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
35 #define M4_BOOTROM_BASE_ADDR 0x007F8000
38 #define CAAM_ARB_BASE_ADDR 0x00100000
39 #define CAAM_ARB_END_ADDR 0x00103FFF
40 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
41 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
42 #define HDMI_ARB_BASE_ADDR 0x00120000
43 #define HDMI_ARB_END_ADDR 0x00128FFF
44 #define GPU_3D_ARB_BASE_ADDR 0x00130000
45 #define GPU_3D_ARB_END_ADDR 0x00133FFF
46 #define GPU_2D_ARB_BASE_ADDR 0x00134000
47 #define GPU_2D_ARB_END_ADDR 0x00137FFF
48 #define DTCP_ARB_BASE_ADDR 0x00138000
49 #define DTCP_ARB_END_ADDR 0x0013BFFF
50 #endif /* CONFIG_SOC_MX6SL */
52 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
53 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
54 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
56 /* GPV - PL301 configuration ports */
57 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
58 #define GPV2_BASE_ADDR 0x00D00000
60 #define GPV2_BASE_ADDR 0x00200000
63 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
64 #define GPV3_BASE_ADDR 0x00E00000
65 #define GPV4_BASE_ADDR 0x00F00000
66 #define GPV5_BASE_ADDR 0x01000000
67 #define GPV6_BASE_ADDR 0x01100000
68 #define PCIE_ARB_BASE_ADDR 0x08000000
69 #define PCIE_ARB_END_ADDR 0x08FFFFFF
72 #define GPV3_BASE_ADDR 0x00300000
73 #define GPV4_BASE_ADDR 0x00800000
74 #define PCIE_ARB_BASE_ADDR 0x01000000
75 #define PCIE_ARB_END_ADDR 0x01FFFFFF
78 #define IRAM_BASE_ADDR 0x00900000
79 #define SCU_BASE_ADDR 0x00A00000
80 #define IC_INTERFACES_BASE_ADDR 0x00A00100
81 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
82 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
83 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
84 #define L2_PL310_BASE 0x00A02000
85 #define GPV0_BASE_ADDR 0x00B00000
86 #define GPV1_BASE_ADDR 0x00C00000
88 #define AIPS1_ARB_BASE_ADDR 0x02000000
89 #define AIPS1_ARB_END_ADDR 0x020FFFFF
90 #define AIPS2_ARB_BASE_ADDR 0x02100000
91 #define AIPS2_ARB_END_ADDR 0x021FFFFF
92 /* AIPS3 only on i.MX6SX */
93 #define AIPS3_ARB_BASE_ADDR 0x02200000
94 #define AIPS3_ARB_END_ADDR 0x022FFFFF
95 #ifdef CONFIG_SOC_MX6SX
96 #define WEIM_ARB_BASE_ADDR 0x50000000
97 #define WEIM_ARB_END_ADDR 0x57FFFFFF
98 #define QSPI0_AMBA_BASE 0x60000000
99 #define QSPI0_AMBA_END 0x6FFFFFFF
100 #define QSPI1_AMBA_BASE 0x70000000
101 #define QSPI1_AMBA_END 0x7FFFFFFF
102 #elif defined(CONFIG_SOC_MX6UL)
103 #define WEIM_ARB_BASE_ADDR 0x50000000
104 #define WEIM_ARB_END_ADDR 0x57FFFFFF
105 #define QSPI0_AMBA_BASE 0x60000000
106 #define QSPI0_AMBA_END 0x6FFFFFFF
108 #define SATA_ARB_BASE_ADDR 0x02200000
109 #define SATA_ARB_END_ADDR 0x02203FFF
110 #define OPENVG_ARB_BASE_ADDR 0x02204000
111 #define OPENVG_ARB_END_ADDR 0x02207FFF
112 #define HSI_ARB_BASE_ADDR 0x02208000
113 #define HSI_ARB_END_ADDR 0x0220BFFF
114 #define IPU1_ARB_BASE_ADDR 0x02400000
115 #define IPU1_ARB_END_ADDR 0x027FFFFF
116 #define IPU2_ARB_BASE_ADDR 0x02800000
117 #define IPU2_ARB_END_ADDR 0x02BFFFFF
118 #define WEIM_ARB_BASE_ADDR 0x08000000
119 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
122 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
123 #define MMDC0_ARB_BASE_ADDR 0x80000000
124 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
125 #define MMDC1_ARB_BASE_ADDR 0xC0000000
126 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
128 #define MMDC0_ARB_BASE_ADDR 0x10000000
129 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
130 #define MMDC1_ARB_BASE_ADDR 0x80000000
131 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
134 #ifndef CONFIG_SOC_MX6SX
135 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
136 #define IPU_SOC_OFFSET 0x00200000
139 /* Defines for Blocks connected via AIPS (SkyBlue) */
140 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
141 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
142 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
143 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
145 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
146 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
147 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
148 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
149 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
150 #ifdef CONFIG_SOC_MX6SL
151 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
152 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
153 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
154 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
155 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
156 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
157 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
158 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
160 #ifndef CONFIG_SOC_MX6SX
161 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
163 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
164 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
165 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
166 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
167 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
168 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
171 #ifndef CONFIG_SOC_MX6SX
172 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
173 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
175 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
177 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
178 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
179 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
180 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
181 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
182 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
183 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
184 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
185 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
186 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
187 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
188 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
189 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
190 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
191 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
192 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
193 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
194 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
195 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
196 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
197 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
198 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
199 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
200 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
201 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
202 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
203 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
204 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
205 #ifdef CONFIG_SOC_MX6SL
206 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
207 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
208 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
209 #elif defined(CONFIG_SOC_MX6SX)
210 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
211 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
212 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
213 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
214 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
215 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
217 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
218 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
219 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
222 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
223 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
224 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
225 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
227 #define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
228 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
230 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
231 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
233 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
234 #ifdef CONFIG_SOC_MX6SL
235 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
237 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
240 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
241 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
242 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
243 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
244 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
245 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
246 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
247 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
248 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
250 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
251 #ifdef CONFIG_SOC_MX6UL
252 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
255 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
258 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
260 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
261 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
262 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
263 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
264 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
265 #ifdef CONFIG_SOC_MX6SX
266 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
268 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
270 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
271 #ifdef CONFIG_SOC_MX6UL
272 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
273 #elif defined(CONFIG_SOC_MX6SX)
274 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
275 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
276 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
277 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
278 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
280 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
281 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
282 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
283 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
285 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
286 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
287 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
288 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
289 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
290 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
291 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
292 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
294 #ifdef CONFIG_SOC_MX6SX
295 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
296 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
297 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
298 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
299 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
300 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
301 #define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
302 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
303 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
304 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
305 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
306 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
307 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
308 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
309 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
310 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
311 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
312 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
313 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
314 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
315 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
316 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
317 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
318 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
320 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
322 /* only for i.MX6SX/UL */
323 #define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
324 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
326 #define CHIP_REV_1_0 0x10
327 #define CHIP_REV_1_2 0x12
328 #define CHIP_REV_1_5 0x15
329 #define CHIP_REV_2_0 0x20
330 #if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
331 #define IRAM_SIZE 0x00040000
333 #define IRAM_SIZE 0x00020000
335 #define IMX_IIM_BASE OCOTP_BASE_ADDR
336 #define FEC_QUIRK_ENET_MAC
338 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
339 #include <asm/types.h>
341 #define SRC_SCR_CORE_1_RESET_OFFSET 14
342 #define SRC_SCR_CORE_1_RESET_MASK (1 << SRC_SCR_CORE_1_RESET_OFFSET)
343 #define SRC_SCR_CORE_2_RESET_OFFSET 15
344 #define SRC_SCR_CORE_2_RESET_MASK (1 << SRC_SCR_CORE_2_RESET_OFFSET)
345 #define SRC_SCR_CORE_3_RESET_OFFSET 16
346 #define SRC_SCR_CORE_3_RESET_MASK (1 << SRC_SCR_CORE_3_RESET_OFFSET)
347 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
348 #define SRC_SCR_CORE_1_ENABLE_MASK (1 << SRC_SCR_CORE_1_ENABLE_OFFSET)
349 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
350 #define SRC_SCR_CORE_2_ENABLE_MASK (1 << SRC_SCR_CORE_2_ENABLE_OFFSET)
351 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
352 #define SRC_SCR_CORE_3_ENABLE_MASK (1 << SRC_SCR_CORE_3_ENABLE_OFFSET)
391 /* System Reset Controller (SRC) */
413 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
414 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
415 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
416 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
419 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
420 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
421 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
422 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
423 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
424 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
425 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
426 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
427 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
428 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
429 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
430 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
431 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
432 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
433 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
434 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
435 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
436 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
437 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
438 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
439 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
440 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
441 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
442 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
443 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
444 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
445 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
446 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
448 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
449 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
450 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
451 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
453 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
454 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
456 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
457 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
459 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
460 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
462 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
463 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
467 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
486 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
487 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
488 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
489 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
491 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
492 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
493 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
494 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
495 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
496 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
498 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
499 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
500 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
501 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
503 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
504 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
505 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
506 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
508 #define IOMUXC_GPR2_BITMAP_SPWG 0
509 #define IOMUXC_GPR2_BITMAP_JEIDA 1
511 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
512 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
513 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
514 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
516 #define IOMUXC_GPR2_DATA_WIDTH_18 0
517 #define IOMUXC_GPR2_DATA_WIDTH_24 1
519 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
520 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
521 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
522 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
524 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
525 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
526 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
527 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
529 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
530 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
531 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
532 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
534 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
535 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
537 #define IOMUXC_GPR2_MODE_DISABLED 0
538 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
539 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
541 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
542 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
543 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
544 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
545 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
547 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
548 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
549 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
550 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
551 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
553 /* ECSPI registers */
566 * CSPI register definitions
569 #define MXC_CSPICTRL_EN (1 << 0)
570 #define MXC_CSPICTRL_MODE (1 << 1)
571 #define MXC_CSPICTRL_XCH (1 << 2)
572 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
573 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
574 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
575 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
576 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
577 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
578 #define MXC_CSPICTRL_MAXBITS 0xfff
579 #define MXC_CSPICTRL_TC (1 << 7)
580 #define MXC_CSPICTRL_RXOVF (1 << 6)
581 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
582 #define MAX_SPI_BYTES 32
583 #define SPI_MAX_NUM 4
585 /* Bit position inside CTRL register to be associated with SS */
586 #define MXC_CSPICTRL_CHAN 18
588 /* Bit position inside CON register to be associated with SS */
589 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
590 #define MXC_CSPICON_POL 4 /* SCLK polarity */
591 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
592 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
593 #if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6UL)
594 #define MXC_SPI_BASE_ADDRESSES \
600 #define MXC_SPI_BASE_ADDRESSES \
613 reg_32(read_fuse_data);
622 reg_32(fuse_regs[8]);
626 struct fuse_bank0_regs {
627 reg_32(misc_conf_lock);
643 struct fuse_bank1_regs {
654 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL))
655 struct fuse_bank4_regs {
656 reg_32(sjc_resp_low);
657 reg_32(sjc_resp_high);
658 reg_32(mac_addr_low);
659 reg_32(mac_addr_high);
666 struct fuse_bank4_regs {
667 reg_32(sjc_resp_low);
668 reg_32(sjc_resp_high);
669 reg_32(mac_addr_low);
670 reg_32(mac_addr_high);
676 struct fuse_bank5_regs {
678 reg_32(pad_settings);
679 reg_32(field_return);
695 mxs_reg_32(pll_arm); /* 0x000 */
696 mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */
697 mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */
698 mxs_reg_32(pll_528); /* 0x030 */
699 reg_32(pll_528_ss); /* 0x040 */
700 reg_32(pll_528_num); /* 0x050 */
701 reg_32(pll_528_denom); /* 0x060 */
702 mxs_reg_32(pll_audio); /* 0x070 */
703 reg_32(pll_audio_num); /* 0x080 */
704 reg_32(pll_audio_denom); /* 0x090 */
705 mxs_reg_32(pll_video); /* 0x0a0 */
706 reg_32(pll_video_num); /* 0x0b0 */
707 reg_32(pll_video_denom); /* 0x0c0 */
708 mxs_reg_32(pll_mlb); /* 0x0d0 */
709 mxs_reg_32(pll_enet); /* 0x0e0 */
710 mxs_reg_32(pfd_480); /* 0x0f0 */
711 mxs_reg_32(pfd_528); /* 0x100 */
712 mxs_reg_32(reg_1p1); /* 0x110 */
713 mxs_reg_32(reg_3p0); /* 0x120 */
714 mxs_reg_32(reg_2p5); /* 0x130 */
715 mxs_reg_32(reg_core); /* 0x140 */
716 mxs_reg_32(ana_misc0); /* 0x150 */
717 mxs_reg_32(ana_misc1); /* 0x160 */
718 mxs_reg_32(ana_misc2); /* 0x170 */
719 mxs_reg_32(tempsense0); /* 0x180 */
720 mxs_reg_32(tempsense1); /* 0x190 */
721 mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */
722 mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */
723 mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
724 mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
725 mxs_reg_32(usb1_loopback); /* 0x1e0 */
726 mxs_reg_32(usb1_misc); /* 0x1f0 */
727 mxs_reg_32(usb2_vbus_detect); /* 0x200 */
728 mxs_reg_32(usb2_chrg_detect); /* 0x210 */
729 mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
730 mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
731 mxs_reg_32(usb2_loopback); /* 0x240 */
732 mxs_reg_32(usb2_misc); /* 0x250 */
733 reg_32(digprog); /* 0x260 */
734 reg_32(rsrvd); /* 0x270 */
735 reg_32(digprog_sololite); /* 0x280 */
738 #define ANATOP_PFD_FRAC_SHIFT(n) ((n) * 8)
739 #define ANATOP_PFD_FRAC_MASK(n) (0x3f << ANATOP_PFD_FRAC_SHIFT(n))
740 #define ANATOP_PFD_STABLE_SHIFT(n) (6 + ((n) * 8))
741 #define ANATOP_PFD_STABLE_MASK(n) (1 << ANATOP_PFD_STABLE_SHIFT(n))
742 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7 + ((n) * 8))
743 #define ANATOP_PFD_CLKGATE_MASK(n) (1 << ANATOP_PFD_CLKGATE_SHIFT(n))
746 u16 wcr; /* Control */
747 u16 wsr; /* Service */
748 u16 wrsr; /* Reset Status */
749 u16 wicr; /* Interrupt Control */
750 u16 wmcr; /* Miscellaneous Control */
753 #define PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
754 #define PWMCR_DOZEEN (1 << 24)
755 #define PWMCR_WAITEN (1 << 23)
756 #define PWMCR_DBGEN (1 << 22)
757 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
758 #define PWMCR_CLKSRC_IPG (1 << 16)
759 #define PWMCR_EN (1 << 0)
769 #endif /* __ASSEMBLER__*/
770 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */