arch/arm/include/asm/arch-mx6/regs-apbh.h

   1 /*
   2  * Freescale i.MX6Q APBH Register Definitions
   3  *
   4  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   5  * based on: arch/arm/include/arch-mx28/apbh-regs.h by Marek Vasut <marek.vasut@gmail.com>
   6  * on behalf of DENX Software Engineering GmbH
   7  *
   8  * Based on code from LTIB:
   9  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24  *
  25  */
  26
  27 #ifndef __REGS_APBH_H__
  28 #define __REGS_APBH_H__
  29
  30 #include <asm/arch/imx-regs.h>
  31
  32 #define MXS_APBH_BASE           0x00110000
  33
  34 #ifndef __ASSEMBLY__
  35 struct apbh_regs {
  36         mx6_reg_32(hw_apbh_ctrl0);                              /* 0x000 */
  37         mx6_reg_32(hw_apbh_ctrl1);                              /* 0x010 */
  38         mx6_reg_32(hw_apbh_ctrl2);                              /* 0x020 */
  39         mx6_reg_32(hw_apbh_channel_ctrl);                       /* 0x030 */
  40         reg_32(hw_apbh_devsel);                                 /* 0x040 */
  41         reg_32(hw_apbh_dma_burst_size);                         /* 0x050 */
  42         reg_32(hw_apbh_debug);                                  /* 0x060 */
  43
  44         reg_32(reserved[9]);                                    /* 0x064-0x0fc */
  45
  46         union {
  47                 struct {
  48                         reg_32(hw_apbh_ch_curcmdar);
  49                         reg_32(hw_apbh_ch_nxtcmdar);
  50                         reg_32(hw_apbh_ch_cmd);
  51                         reg_32(hw_apbh_ch_bar);
  52                         reg_32(hw_apbh_ch_sema);
  53                         reg_32(hw_apbh_ch_debug1);
  54                         reg_32(hw_apbh_ch_debug2);
  55                 } ch[16];
  56                 struct {
  57                         reg_32(hw_apbh_ch0_curcmdar);           /* 0x100 */
  58                         reg_32(hw_apbh_ch0_nxtcmdar);           /* 0x110 */
  59                         reg_32(hw_apbh_ch0_cmd);                /* 0x120 */
  60                         reg_32(hw_apbh_ch0_bar);                /* 0x130 */
  61                         reg_32(hw_apbh_ch0_sema);               /* 0x140 */
  62                         reg_32(hw_apbh_ch0_debug1);             /* 0x150 */
  63                         reg_32(hw_apbh_ch0_debug2);             /* 0x160 */
  64                         reg_32(hw_apbh_ch1_curcmdar);           /* 0x170 */
  65                         reg_32(hw_apbh_ch1_nxtcmdar);           /* 0x180 */
  66                         reg_32(hw_apbh_ch1_cmd);                /* 0x190 */
  67                         reg_32(hw_apbh_ch1_bar);                /* 0x1a0 */
  68                         reg_32(hw_apbh_ch1_sema);               /* 0x1b0 */
  69                         reg_32(hw_apbh_ch1_debug1);             /* 0x1c0 */
  70                         reg_32(hw_apbh_ch1_debug2);             /* 0x1d0 */
  71                         reg_32(hw_apbh_ch2_curcmdar);           /* 0x1e0 */
  72                         reg_32(hw_apbh_ch2_nxtcmdar);           /* 0x1f0 */
  73                         reg_32(hw_apbh_ch2_cmd);                /* 0x200 */
  74                         reg_32(hw_apbh_ch2_bar);                /* 0x210 */
  75                         reg_32(hw_apbh_ch2_sema);               /* 0x220 */
  76                         reg_32(hw_apbh_ch2_debug1);             /* 0x230 */
  77                         reg_32(hw_apbh_ch2_debug2);             /* 0x240 */
  78                         reg_32(hw_apbh_ch3_curcmdar);           /* 0x250 */
  79                         reg_32(hw_apbh_ch3_nxtcmdar);           /* 0x260 */
  80                         reg_32(hw_apbh_ch3_cmd);                /* 0x270 */
  81                         reg_32(hw_apbh_ch3_bar);                /* 0x280 */
  82                         reg_32(hw_apbh_ch3_sema);               /* 0x290 */
  83                         reg_32(hw_apbh_ch3_debug1);             /* 0x2a0 */
  84                         reg_32(hw_apbh_ch3_debug2);             /* 0x2b0 */
  85                         reg_32(hw_apbh_ch4_curcmdar);           /* 0x2c0 */
  86                         reg_32(hw_apbh_ch4_nxtcmdar);           /* 0x2d0 */
  87                         reg_32(hw_apbh_ch4_cmd);                /* 0x2e0 */
  88                         reg_32(hw_apbh_ch4_bar);                /* 0x2f0 */
  89                         reg_32(hw_apbh_ch4_sema);               /* 0x300 */
  90                         reg_32(hw_apbh_ch4_debug1);             /* 0x310 */
  91                         reg_32(hw_apbh_ch4_debug2);             /* 0x320 */
  92                         reg_32(hw_apbh_ch5_curcmdar);           /* 0x330 */
  93                         reg_32(hw_apbh_ch5_nxtcmdar);           /* 0x340 */
  94                         reg_32(hw_apbh_ch5_cmd);                /* 0x350 */
  95                         reg_32(hw_apbh_ch5_bar);                /* 0x360 */
  96                         reg_32(hw_apbh_ch5_sema);               /* 0x370 */
  97                         reg_32(hw_apbh_ch5_debug1);             /* 0x380 */
  98                         reg_32(hw_apbh_ch5_debug2);             /* 0x390 */
  99                         reg_32(hw_apbh_ch6_curcmdar);           /* 0x3a0 */
 100                         reg_32(hw_apbh_ch6_nxtcmdar);           /* 0x3b0 */
 101                         reg_32(hw_apbh_ch6_cmd);                /* 0x3c0 */
 102                         reg_32(hw_apbh_ch6_bar);                /* 0x3d0 */
 103                         reg_32(hw_apbh_ch6_sema);               /* 0x3e0 */
 104                         reg_32(hw_apbh_ch6_debug1);             /* 0x3f0 */
 105                         reg_32(hw_apbh_ch6_debug2);             /* 0x400 */
 106                         reg_32(hw_apbh_ch7_curcmdar);           /* 0x410 */
 107                         reg_32(hw_apbh_ch7_nxtcmdar);           /* 0x420 */
 108                         reg_32(hw_apbh_ch7_cmd);                /* 0x430 */
 109                         reg_32(hw_apbh_ch7_bar);                /* 0x440 */
 110                         reg_32(hw_apbh_ch7_sema);               /* 0x450 */
 111                         reg_32(hw_apbh_ch7_debug1);             /* 0x460 */
 112                         reg_32(hw_apbh_ch7_debug2);             /* 0x470 */
 113                         reg_32(hw_apbh_ch8_curcmdar);           /* 0x480 */
 114                         reg_32(hw_apbh_ch8_nxtcmdar);           /* 0x490 */
 115                         reg_32(hw_apbh_ch8_cmd);                /* 0x4a0 */
 116                         reg_32(hw_apbh_ch8_bar);                /* 0x4b0 */
 117                         reg_32(hw_apbh_ch8_sema);               /* 0x4c0 */
 118                         reg_32(hw_apbh_ch8_debug1);             /* 0x4d0 */
 119                         reg_32(hw_apbh_ch8_debug2);             /* 0x4e0 */
 120                         reg_32(hw_apbh_ch9_curcmdar);           /* 0x4f0 */
 121                         reg_32(hw_apbh_ch9_nxtcmdar);           /* 0x500 */
 122                         reg_32(hw_apbh_ch9_cmd);                /* 0x510 */
 123                         reg_32(hw_apbh_ch9_bar);                /* 0x520 */
 124                         reg_32(hw_apbh_ch9_sema);               /* 0x530 */
 125                         reg_32(hw_apbh_ch9_debug1);             /* 0x540 */
 126                         reg_32(hw_apbh_ch9_debug2);             /* 0x550 */
 127                         reg_32(hw_apbh_ch10_curcmdar);          /* 0x560 */
 128                         reg_32(hw_apbh_ch10_nxtcmdar);          /* 0x570 */
 129                         reg_32(hw_apbh_ch10_cmd);               /* 0x580 */
 130                         reg_32(hw_apbh_ch10_bar);               /* 0x590 */
 131                         reg_32(hw_apbh_ch10_sema);              /* 0x5a0 */
 132                         reg_32(hw_apbh_ch10_debug1);            /* 0x5b0 */
 133                         reg_32(hw_apbh_ch10_debug2);            /* 0x5c0 */
 134                         reg_32(hw_apbh_ch11_curcmdar);          /* 0x5d0 */
 135                         reg_32(hw_apbh_ch11_nxtcmdar);          /* 0x5e0 */
 136                         reg_32(hw_apbh_ch11_cmd);               /* 0x5f0 */
 137                         reg_32(hw_apbh_ch11_bar);               /* 0x600 */
 138                         reg_32(hw_apbh_ch11_sema);              /* 0x610 */
 139                         reg_32(hw_apbh_ch11_debug1);            /* 0x620 */
 140                         reg_32(hw_apbh_ch11_debug2);            /* 0x630 */
 141                         reg_32(hw_apbh_ch12_curcmdar);          /* 0x640 */
 142                         reg_32(hw_apbh_ch12_nxtcmdar);          /* 0x650 */
 143                         reg_32(hw_apbh_ch12_cmd);               /* 0x660 */
 144                         reg_32(hw_apbh_ch12_bar);               /* 0x670 */
 145                         reg_32(hw_apbh_ch12_sema);              /* 0x680 */
 146                         reg_32(hw_apbh_ch12_debug1);            /* 0x690 */
 147                         reg_32(hw_apbh_ch12_debug2);            /* 0x6a0 */
 148                         reg_32(hw_apbh_ch13_curcmdar);          /* 0x6b0 */
 149                         reg_32(hw_apbh_ch13_nxtcmdar);          /* 0x6c0 */
 150                         reg_32(hw_apbh_ch13_cmd);               /* 0x6d0 */
 151                         reg_32(hw_apbh_ch13_bar);               /* 0x6e0 */
 152                         reg_32(hw_apbh_ch13_sema);              /* 0x6f0 */
 153                         reg_32(hw_apbh_ch13_debug1);            /* 0x700 */
 154                         reg_32(hw_apbh_ch13_debug2);            /* 0x710 */
 155                         reg_32(hw_apbh_ch14_curcmdar);          /* 0x720 */
 156                         reg_32(hw_apbh_ch14_nxtcmdar);          /* 0x730 */
 157                         reg_32(hw_apbh_ch14_cmd);               /* 0x740 */
 158                         reg_32(hw_apbh_ch14_bar);               /* 0x750 */
 159                         reg_32(hw_apbh_ch14_sema);              /* 0x760 */
 160                         reg_32(hw_apbh_ch14_debug1);            /* 0x770 */
 161                         reg_32(hw_apbh_ch14_debug2);            /* 0x780 */
 162                         reg_32(hw_apbh_ch15_curcmdar);          /* 0x790 */
 163                         reg_32(hw_apbh_ch15_nxtcmdar);          /* 0x7a0 */
 164                         reg_32(hw_apbh_ch15_cmd);               /* 0x7b0 */
 165                         reg_32(hw_apbh_ch15_bar);               /* 0x7c0 */
 166                         reg_32(hw_apbh_ch15_sema);              /* 0x7d0 */
 167                         reg_32(hw_apbh_ch15_debug1);            /* 0x7e0 */
 168                         reg_32(hw_apbh_ch15_debug2);            /* 0x7f0 */
 169                 };
 170         };
 171         mx6_reg_32(hw_apbh_version);                            /* 0x800 */
 172 };
 173 #endif
 174
 175 #define APBH_CTRL0_SFTRST                               (1 << 31)
 176 #define APBH_CTRL0_CLKGATE                              (1 << 30)
 177 #define APBH_CTRL0_AHB_BURST8_EN                        (1 << 29)
 178 #define APBH_CTRL0_APB_BURST_EN                         (1 << 28)
 179 #define APBH_CTRL0_RSVD0_MASK                           (0xfff << 16)
 180 #define APBH_CTRL0_RSVD0_OFFSET                         16
 181 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK                 0xffff
 182 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
 183 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0                 0x0001
 184 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1                 0x0002
 185 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP2                 0x0004
 186 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP3                 0x0008
 187 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0010
 188 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0020
 189 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x0040
 190 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x0080
 191 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4                0x0100
 192 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5                0x0200
 193 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6                0x0400
 194 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
 195 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
 196 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000
 197
 198 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN                 (1 << 31)
 199 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN                 (1 << 30)
 200 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN                 (1 << 29)
 201 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN                 (1 << 28)
 202 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN                 (1 << 27)
 203 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN                 (1 << 26)
 204 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN                  (1 << 25)
 205 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN                  (1 << 24)
 206 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN                  (1 << 23)
 207 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN                  (1 << 22)
 208 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN                  (1 << 21)
 209 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN                  (1 << 20)
 210 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN                  (1 << 19)
 211 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN                  (1 << 18)
 212 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN                  (1 << 17)
 213 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN                  (1 << 16)
 214 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET            16
 215 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK              (0xffff << 16)
 216 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ                    (1 << 15)
 217 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ                    (1 << 14)
 218 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ                    (1 << 13)
 219 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ                    (1 << 12)
 220 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ                    (1 << 11)
 221 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ                    (1 << 10)
 222 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ                     (1 << 9)
 223 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ                     (1 << 8)
 224 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ                     (1 << 7)
 225 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ                     (1 << 6)
 226 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ                     (1 << 5)
 227 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ                     (1 << 4)
 228 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ                     (1 << 3)
 229 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ                     (1 << 2)
 230 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ                     (1 << 1)
 231 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ                     (1 << 0)
 232
 233 #define APBH_CTRL2_CH15_ERROR_STATUS                    (1 << 31)
 234 #define APBH_CTRL2_CH14_ERROR_STATUS                    (1 << 30)
 235 #define APBH_CTRL2_CH13_ERROR_STATUS                    (1 << 29)
 236 #define APBH_CTRL2_CH12_ERROR_STATUS                    (1 << 28)
 237 #define APBH_CTRL2_CH11_ERROR_STATUS                    (1 << 27)
 238 #define APBH_CTRL2_CH10_ERROR_STATUS                    (1 << 26)
 239 #define APBH_CTRL2_CH9_ERROR_STATUS                     (1 << 25)
 240 #define APBH_CTRL2_CH8_ERROR_STATUS                     (1 << 24)
 241 #define APBH_CTRL2_CH7_ERROR_STATUS                     (1 << 23)
 242 #define APBH_CTRL2_CH6_ERROR_STATUS                     (1 << 22)
 243 #define APBH_CTRL2_CH5_ERROR_STATUS                     (1 << 21)
 244 #define APBH_CTRL2_CH4_ERROR_STATUS                     (1 << 20)
 245 #define APBH_CTRL2_CH3_ERROR_STATUS                     (1 << 19)
 246 #define APBH_CTRL2_CH2_ERROR_STATUS                     (1 << 18)
 247 #define APBH_CTRL2_CH1_ERROR_STATUS                     (1 << 17)
 248 #define APBH_CTRL2_CH0_ERROR_STATUS                     (1 << 16)
 249 #define APBH_CTRL2_CH15_ERROR_IRQ                       (1 << 15)
 250 #define APBH_CTRL2_CH14_ERROR_IRQ                       (1 << 14)
 251 #define APBH_CTRL2_CH13_ERROR_IRQ                       (1 << 13)
 252 #define APBH_CTRL2_CH12_ERROR_IRQ                       (1 << 12)
 253 #define APBH_CTRL2_CH11_ERROR_IRQ                       (1 << 11)
 254 #define APBH_CTRL2_CH10_ERROR_IRQ                       (1 << 10)
 255 #define APBH_CTRL2_CH9_ERROR_IRQ                        (1 << 9)
 256 #define APBH_CTRL2_CH8_ERROR_IRQ                        (1 << 8)
 257 #define APBH_CTRL2_CH7_ERROR_IRQ                        (1 << 7)
 258 #define APBH_CTRL2_CH6_ERROR_IRQ                        (1 << 6)
 259 #define APBH_CTRL2_CH5_ERROR_IRQ                        (1 << 5)
 260 #define APBH_CTRL2_CH4_ERROR_IRQ                        (1 << 4)
 261 #define APBH_CTRL2_CH3_ERROR_IRQ                        (1 << 3)
 262 #define APBH_CTRL2_CH2_ERROR_IRQ                        (1 << 2)
 263 #define APBH_CTRL2_CH1_ERROR_IRQ                        (1 << 1)
 264 #define APBH_CTRL2_CH0_ERROR_IRQ                        (1 << 0)
 265
 266 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK            (0xffff << 16)
 267 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
 268 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0            (0x0001 << 16)
 269 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1            (0x0002 << 16)
 270 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2            (0x0004 << 16)
 271 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3            (0x0008 << 16)
 272 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0           (0x0010 << 16)
 273 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1           (0x0020 << 16)
 274 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2           (0x0040 << 16)
 275 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3           (0x0080 << 16)
 276 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4           (0x0100 << 16)
 277 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5           (0x0200 << 16)
 278 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6           (0x0400 << 16)
 279 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7           (0x0800 << 16)
 280 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC           (0x1000 << 16)
 281 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF           (0x2000 << 16)
 282 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK           0xffff
 283 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET         0
 284 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0           0x0001
 285 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1           0x0002
 286 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2           0x0004
 287 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3           0x0008
 288 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0          0x0010
 289 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1          0x0020
 290 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2          0x0040
 291 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3          0x0080
 292 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4          0x0100
 293 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5          0x0200
 294 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6          0x0400
 295 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7          0x0800
 296 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC          0x1000
 297 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
 298
 299 #define APBH_DEVSEL_CH15_MASK                           (0x3 << 30)
 300 #define APBH_DEVSEL_CH15_OFFSET                         30
 301 #define APBH_DEVSEL_CH14_MASK                           (0x3 << 28)
 302 #define APBH_DEVSEL_CH14_OFFSET                         28
 303 #define APBH_DEVSEL_CH13_MASK                           (0x3 << 26)
 304 #define APBH_DEVSEL_CH13_OFFSET                         26
 305 #define APBH_DEVSEL_CH12_MASK                           (0x3 << 24)
 306 #define APBH_DEVSEL_CH12_OFFSET                         24
 307 #define APBH_DEVSEL_CH11_MASK                           (0x3 << 22)
 308 #define APBH_DEVSEL_CH11_OFFSET                         22
 309 #define APBH_DEVSEL_CH10_MASK                           (0x3 << 20)
 310 #define APBH_DEVSEL_CH10_OFFSET                         20
 311 #define APBH_DEVSEL_CH9_MASK                            (0x3 << 18)
 312 #define APBH_DEVSEL_CH9_OFFSET                          18
 313 #define APBH_DEVSEL_CH8_MASK                            (0x3 << 16)
 314 #define APBH_DEVSEL_CH8_OFFSET                          16
 315 #define APBH_DEVSEL_CH7_MASK                            (0x3 << 14)
 316 #define APBH_DEVSEL_CH7_OFFSET                          14
 317 #define APBH_DEVSEL_CH6_MASK                            (0x3 << 12)
 318 #define APBH_DEVSEL_CH6_OFFSET                          12
 319 #define APBH_DEVSEL_CH5_MASK                            (0x3 << 10)
 320 #define APBH_DEVSEL_CH5_OFFSET                          10
 321 #define APBH_DEVSEL_CH4_MASK                            (0x3 << 8)
 322 #define APBH_DEVSEL_CH4_OFFSET                          8
 323 #define APBH_DEVSEL_CH3_MASK                            (0x3 << 6)
 324 #define APBH_DEVSEL_CH3_OFFSET                          6
 325 #define APBH_DEVSEL_CH2_MASK                            (0x3 << 4)
 326 #define APBH_DEVSEL_CH2_OFFSET                          4
 327 #define APBH_DEVSEL_CH1_MASK                            (0x3 << 2)
 328 #define APBH_DEVSEL_CH1_OFFSET                          2
 329 #define APBH_DEVSEL_CH0_MASK                            (0x3 << 0)
 330 #define APBH_DEVSEL_CH0_OFFSET                          0
 331
 332 #define APBH_DMA_BURST_SIZE_CH15_MASK                   (0x3 << 30)
 333 #define APBH_DMA_BURST_SIZE_CH15_OFFSET                 30
 334 #define APBH_DMA_BURST_SIZE_CH14_MASK                   (0x3 << 28)
 335 #define APBH_DMA_BURST_SIZE_CH14_OFFSET                 28
 336 #define APBH_DMA_BURST_SIZE_CH13_MASK                   (0x3 << 26)
 337 #define APBH_DMA_BURST_SIZE_CH13_OFFSET                 26
 338 #define APBH_DMA_BURST_SIZE_CH12_MASK                   (0x3 << 24)
 339 #define APBH_DMA_BURST_SIZE_CH12_OFFSET                 24
 340 #define APBH_DMA_BURST_SIZE_CH11_MASK                   (0x3 << 22)
 341 #define APBH_DMA_BURST_SIZE_CH11_OFFSET                 22
 342 #define APBH_DMA_BURST_SIZE_CH10_MASK                   (0x3 << 20)
 343 #define APBH_DMA_BURST_SIZE_CH10_OFFSET                 20
 344 #define APBH_DMA_BURST_SIZE_CH9_MASK                    (0x3 << 18)
 345 #define APBH_DMA_BURST_SIZE_CH9_OFFSET                  18
 346 #define APBH_DMA_BURST_SIZE_CH8_MASK                    (0x3 << 16)
 347 #define APBH_DMA_BURST_SIZE_CH8_OFFSET                  16
 348 #define APBH_DMA_BURST_SIZE_CH8_BURST0                  (0x0 << 16)
 349 #define APBH_DMA_BURST_SIZE_CH8_BURST4                  (0x1 << 16)
 350 #define APBH_DMA_BURST_SIZE_CH8_BURST8                  (0x2 << 16)
 351 #define APBH_DMA_BURST_SIZE_CH7_MASK                    (0x3 << 14)
 352 #define APBH_DMA_BURST_SIZE_CH7_OFFSET                  14
 353 #define APBH_DMA_BURST_SIZE_CH6_MASK                    (0x3 << 12)
 354 #define APBH_DMA_BURST_SIZE_CH6_OFFSET                  12
 355 #define APBH_DMA_BURST_SIZE_CH5_MASK                    (0x3 << 10)
 356 #define APBH_DMA_BURST_SIZE_CH5_OFFSET                  10
 357 #define APBH_DMA_BURST_SIZE_CH4_MASK                    (0x3 << 8)
 358 #define APBH_DMA_BURST_SIZE_CH4_OFFSET                  8
 359 #define APBH_DMA_BURST_SIZE_CH3_MASK                    (0x3 << 6)
 360 #define APBH_DMA_BURST_SIZE_CH3_OFFSET                  6
 361 #define APBH_DMA_BURST_SIZE_CH3_BURST0                  (0x0 << 6)
 362 #define APBH_DMA_BURST_SIZE_CH3_BURST4                  (0x1 << 6)
 363 #define APBH_DMA_BURST_SIZE_CH3_BURST8                  (0x2 << 6)
 364
 365 #define APBH_DMA_BURST_SIZE_CH2_MASK                    (0x3 << 4)
 366 #define APBH_DMA_BURST_SIZE_CH2_OFFSET                  4
 367 #define APBH_DMA_BURST_SIZE_CH2_BURST0                  (0x0 << 4)
 368 #define APBH_DMA_BURST_SIZE_CH2_BURST4                  (0x1 << 4)
 369 #define APBH_DMA_BURST_SIZE_CH2_BURST8                  (0x2 << 4)
 370 #define APBH_DMA_BURST_SIZE_CH1_MASK                    (0x3 << 2)
 371 #define APBH_DMA_BURST_SIZE_CH1_OFFSET                  2
 372 #define APBH_DMA_BURST_SIZE_CH1_BURST0                  (0x0 << 2)
 373 #define APBH_DMA_BURST_SIZE_CH1_BURST4                  (0x1 << 2)
 374 #define APBH_DMA_BURST_SIZE_CH1_BURST8                  (0x2 << 2)
 375
 376 #define APBH_DMA_BURST_SIZE_CH0_MASK                    0x3
 377 #define APBH_DMA_BURST_SIZE_CH0_OFFSET                  0
 378 #define APBH_DMA_BURST_SIZE_CH0_BURST0                  0x0
 379 #define APBH_DMA_BURST_SIZE_CH0_BURST4                  0x1
 380 #define APBH_DMA_BURST_SIZE_CH0_BURST8                  0x2
 381
 382 #define APBH_DEBUG_GPMI_ONE_FIFO                        (1 << 0)
 383
 384 #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK                 0xffffffff
 385 #define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET               0
 386
 387 #define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK                 0xffffffff
 388 #define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET               0
 389
 390 #define APBH_CHn_CMD_XFER_COUNT_MASK                    (0xffff << 16)
 391 #define APBH_CHn_CMD_XFER_COUNT_OFFSET                  16
 392 #define APBH_CHn_CMD_CMDWORDS_MASK                      (0xf << 12)
 393 #define APBH_CHn_CMD_CMDWORDS_OFFSET                    12
 394 #define APBH_CHn_CMD_HALTONTERMINATE                    (1 << 8)
 395 #define APBH_CHn_CMD_WAIT4ENDCMD                        (1 << 7)
 396 #define APBH_CHn_CMD_SEMAPHORE                          (1 << 6)
 397 #define APBH_CHn_CMD_NANDWAIT4READY                     (1 << 5)
 398 #define APBH_CHn_CMD_NANDLOCK                           (1 << 4)
 399 #define APBH_CHn_CMD_IRQONCMPLT                         (1 << 3)
 400 #define APBH_CHn_CMD_CHAIN                              (1 << 2)
 401 #define APBH_CHn_CMD_COMMAND_MASK                       0x3
 402 #define APBH_CHn_CMD_COMMAND_OFFSET                     0
 403 #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER                0x0
 404 #define APBH_CHn_CMD_COMMAND_DMA_WRITE                  0x1
 405 #define APBH_CHn_CMD_COMMAND_DMA_READ                   0x2
 406 #define APBH_CHn_CMD_COMMAND_DMA_SENSE                  0x3
 407
 408 #define APBH_CHn_BAR_ADDRESS_MASK                       0xffffffff
 409 #define APBH_CHn_BAR_ADDRESS_OFFSET                     0
 410
 411 #define APBH_CHn_SEMA_RSVD2_MASK                        (0xff << 24)
 412 #define APBH_CHn_SEMA_RSVD2_OFFSET                      24
 413 #define APBH_CHn_SEMA_PHORE_MASK                        (0xff << 16)
 414 #define APBH_CHn_SEMA_PHORE_OFFSET                      16
 415 #define APBH_CHn_SEMA_RSVD1_MASK                        (0xff << 8)
 416 #define APBH_CHn_SEMA_RSVD1_OFFSET                      8
 417 #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK               (0xff << 0)
 418 #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET             0
 419
 420 #define APBH_CHn_DEBUG1_REQ                             (1 << 31)
 421 #define APBH_CHn_DEBUG1_BURST                           (1 << 30)
 422 #define APBH_CHn_DEBUG1_KICK                            (1 << 29)
 423 #define APBH_CHn_DEBUG1_END                             (1 << 28)
 424 #define APBH_CHn_DEBUG1_SENSE                           (1 << 27)
 425 #define APBH_CHn_DEBUG1_READY                           (1 << 26)
 426 #define APBH_CHn_DEBUG1_LOCK                            (1 << 25)
 427 #define APBH_CHn_DEBUG1_NEXTCMDADDRVALID                (1 << 24)
 428 #define APBH_CHn_DEBUG1_RD_FIFO_EMPTY                   (1 << 23)
 429 #define APBH_CHn_DEBUG1_RD_FIFO_FULL                    (1 << 22)
 430 #define APBH_CHn_DEBUG1_WR_FIFO_EMPTY                   (1 << 21)
 431 #define APBH_CHn_DEBUG1_WR_FIFO_FULL                    (1 << 20)
 432 #define APBH_CHn_DEBUG1_RSVD1_MASK                      (0x7fff << 5)
 433 #define APBH_CHn_DEBUG1_RSVD1_OFFSET                    5
 434 #define APBH_CHn_DEBUG1_STATEMACHINE_MASK               0x1f
 435 #define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET             0
 436 #define APBH_CHn_DEBUG1_STATEMACHINE_IDLE               0x00
 437 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1           0x01
 438 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3           0x02
 439 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2           0x03
 440 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE        0x04
 441 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT           0x05
 442 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4           0x06
 443 #define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ            0x07
 444 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH         0x08
 445 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT          0x09
 446 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE              0x0c
 447 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ           0x0d
 448 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN        0x0e
 449 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE      0x0f
 450 #define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE          0x14
 451 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END           0x15
 452 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT         0x1c
 453 #define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM    0x1d
 454 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT         0x1e
 455 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY         0x1f
 456
 457 #define APBH_CHn_DEBUG2_APB_BYTES_MASK                  (0xffff << 16)
 458 #define APBH_CHn_DEBUG2_APB_BYTES_OFFSET                16
 459 #define APBH_CHn_DEBUG2_AHB_BYTES_MASK                  0xffff
 460 #define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET                0
 461
 462 #define APBH_VERSION_MAJOR_MASK                         (0xff << 24)
 463 #define APBH_VERSION_MAJOR_OFFSET                       24
 464 #define APBH_VERSION_MINOR_MASK                         (0xff << 16)
 465 #define APBH_VERSION_MINOR_OFFSET                       16
 466 #define APBH_VERSION_STEP_MASK                          0xffff
 467 #define APBH_VERSION_STEP_OFFSET                        0
 468
 469 #endif  /* __REGS_APBH_H__ */