arch/arm/include/asm/arch-mx6/regs-lcdif.h

   1 /*
   2  * Freescale i.MX6SL,SX,UL LCDIF Register Definitions
   3  *
   4  * Copyright (C) 2015 Lothar Waßmann <LW@karo-electronics.de>
   5  * based on: arch/arm/include/asm/arch-mxs/regs-lcdif.h
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __MX6_REGS_LCDIF_H__
  11 #define __MX6_REGS_LCDIF_H__
  12
  13 #include <asm/imx-common/regs-common.h>
  14
  15 #ifndef __ASSEMBLY__
  16 struct mxs_lcdif_regs {
  17         mxs_reg_32(hw_lcdif_ctrl);              /* 0x00 */
  18         mxs_reg_32(hw_lcdif_ctrl1);             /* 0x10 */
  19         mxs_reg_32(hw_lcdif_ctrl2)              /* 0x20 */
  20         mxs_reg_32(hw_lcdif_transfer_count);    /* 0x30 */
  21         mxs_reg_32(hw_lcdif_cur_buf);           /* 0x40 */
  22         mxs_reg_32(hw_lcdif_next_buf);          /* 0x50 */
  23         mxs_reg_32(hw_lcdif_timing);            /* 0x60 */
  24         mxs_reg_32(hw_lcdif_vdctrl0);           /* 0x70 */
  25         mxs_reg_32(hw_lcdif_vdctrl1);           /* 0x80 */
  26         mxs_reg_32(hw_lcdif_vdctrl2);           /* 0x90 */
  27         mxs_reg_32(hw_lcdif_vdctrl3);           /* 0xa0 */
  28         mxs_reg_32(hw_lcdif_vdctrl4);           /* 0xb0 */
  29         mxs_reg_32(hw_lcdif_dvictrl0);          /* 0xc0 */
  30         mxs_reg_32(hw_lcdif_dvictrl1);          /* 0xd0 */
  31         mxs_reg_32(hw_lcdif_dvictrl2);          /* 0xe0 */
  32         mxs_reg_32(hw_lcdif_dvictrl3);          /* 0xf0 */
  33         mxs_reg_32(hw_lcdif_dvictrl4);          /* 0x100 */
  34         mxs_reg_32(hw_lcdif_csc_coeffctrl0);    /* 0x110 */
  35         mxs_reg_32(hw_lcdif_csc_coeffctrl1);    /* 0x120 */
  36         mxs_reg_32(hw_lcdif_csc_coeffctrl2);    /* 0x130 */
  37         mxs_reg_32(hw_lcdif_csc_coeffctrl3);    /* 0x140 */
  38         mxs_reg_32(hw_lcdif_csc_coeffctrl4);    /* 0x150 */
  39         mxs_reg_32(hw_lcdif_csc_offset);        /* 0x160 */
  40         mxs_reg_32(hw_lcdif_csc_limit);         /* 0x170 */
  41         mxs_reg_32(hw_lcdif_data)               /* 0x180 */
  42         mxs_reg_32(hw_lcdif_bm_error_stat)      /* 0x190 */
  43         mxs_reg_32(hw_lcdif_crc_stat)           /* 0x1a0 */
  44         mxs_reg_32(hw_lcdif_lcdif_stat);        /* 0x1b0 */
  45         mxs_reg_32(hw_lcdif_version);           /* 0x1c0 */
  46         mxs_reg_32(hw_lcdif_debug0);            /* 0x1d0 */
  47         mxs_reg_32(hw_lcdif_debug1);            /* 0x1e0 */
  48         mxs_reg_32(hw_lcdif_debug2);            /* 0x1f0 */
  49         mxs_reg_32(hw_elcdif_thresh);           /* 0x200 */
  50         mxs_reg_32(hw_elcdif_as_ctrl);          /* 0x210 */
  51         mxs_reg_32(hw_elcdif_as_buf);           /* 0x220 */
  52         mxs_reg_32(hw_elcdif_as_next_buf);      /* 0x230 */
  53         mxs_reg_32(hw_elcdif_as_clrkeylow);     /* 0x240 */
  54         mxs_reg_32(hw_elcdif_as_clrkeyhigh);    /* 0x250 */
  55         mxs_reg_32(hw_elcdif_sync_delay);       /* 0x260 */
  56         mxs_reg_32(hw_elcdif_debug3);           /* 0x270 */
  57         mxs_reg_32(hw_lcdif_debug4);            /* 0x280 */
  58         mxs_reg_32(hw_lcdif_debug5);            /* 0x290 */
  59 };
  60 #endif
  61
  62 #define LCDIF_CTRL_SFTRST                                       (1 << 31)
  63 #define LCDIF_CTRL_CLKGATE                                      (1 << 30)
  64 #define LCDIF_CTRL_YCBCR422_INPUT                               (1 << 29)
  65 #define LCDIF_CTRL_READ_WRITEB                                  (1 << 28)
  66 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                          (1 << 27)
  67 #define LCDIF_CTRL_DATA_SHIFT_DIR                               (1 << 26)
  68 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK                          (0x1f << 21)
  69 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET                        21
  70 #define LCDIF_CTRL_DVI_MODE                                     (1 << 20)
  71 #define LCDIF_CTRL_BYPASS_COUNT                                 (1 << 19)
  72 #define LCDIF_CTRL_VSYNC_MODE                                   (1 << 18)
  73 #define LCDIF_CTRL_DOTCLK_MODE                                  (1 << 17)
  74 #define LCDIF_CTRL_DATA_SELECT                                  (1 << 16)
  75 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK                      (0x3 << 14)
  76 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET                    14
  77 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK                        (0x3 << 12)
  78 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET                      12
  79 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK                       (0x3 << 10)
  80 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET                     10
  81 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT                      (0 << 10)
  82 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT                       (1 << 10)
  83 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT                      (2 << 10)
  84 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT                      (3 << 10)
  85 #define LCDIF_CTRL_WORD_LENGTH_MASK                             (0x3 << 8)
  86 #define LCDIF_CTRL_WORD_LENGTH_OFFSET                           8
  87 #define LCDIF_CTRL_WORD_LENGTH_16BIT                            (0 << 8)
  88 #define LCDIF_CTRL_WORD_LENGTH_8BIT                             (1 << 8)
  89 #define LCDIF_CTRL_WORD_LENGTH_18BIT                            (2 << 8)
  90 #define LCDIF_CTRL_WORD_LENGTH_24BIT                            (3 << 8)
  91 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC                          (1 << 7)
  92 #define LCDIF_CTRL_LCDIF_MASTER                                 (1 << 5)
  93 #define LCDIF_CTRL_DATA_FORMAT_16_BIT                           (1 << 3)
  94 #define LCDIF_CTRL_DATA_FORMAT_18_BIT                           (1 << 2)
  95 #define LCDIF_CTRL_DATA_FORMAT_24_BIT                           (1 << 1)
  96 #define LCDIF_CTRL_RUN                                          (1 << 0)
  97
  98 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB                         (1 << 27)
  99 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN                             (1 << 26)
 100 #define LCDIF_CTRL1_BM_ERROR_IRQ                                (1 << 25)
 101 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                        (1 << 24)
 102 #define LCDIF_CTRL1_INTERLACE_FIELDS                            (1 << 23)
 103 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD           (1 << 22)
 104 #define LCDIF_CTRL1_FIFO_CLEAR                                  (1 << 21)
 105 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS                     (1 << 20)
 106 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK                    (0xf << 16)
 107 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET                  16
 108 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n)                      (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \
 109                                                 LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
 110 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN                             (1 << 15)
 111 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN                            (1 << 14)
 112 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                       (1 << 13)
 113 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                           (1 << 12)
 114 #define LCDIF_CTRL1_OVERFLOW_IRQ                                (1 << 11)
 115 #define LCDIF_CTRL1_UNDERFLOW_IRQ                               (1 << 10)
 116 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                          (1 << 9)
 117 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ                              (1 << 8)
 118 #define LCDIF_CTRL1_BUSY_ENABLE                                 (1 << 2)
 119 #define LCDIF_CTRL1_MODE86                                      (1 << 1)
 120 #define LCDIF_CTRL1_RESET                                       (1 << 0)
 121
 122 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK                       (0x7 << 21)
 123 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET                     21
 124 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1                      (0x0 << 21)
 125 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2                      (0x1 << 21)
 126 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4                      (0x2 << 21)
 127 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8                      (0x3 << 21)
 128 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16                     (0x4 << 21)
 129 #define LCDIF_CTRL2_BURST_LEN_8                                 (1 << 20)
 130 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK                       (0x7 << 16)
 131 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET                     16
 132 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB                        (0x0 << 16)
 133 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG                        (0x1 << 16)
 134 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR                        (0x2 << 16)
 135 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB                        (0x3 << 16)
 136 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG                        (0x4 << 16)
 137 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR                        (0x5 << 16)
 138 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK                      (0x7 << 12)
 139 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET                    12
 140 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB                       (0x0 << 12)
 141 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG                       (0x1 << 12)
 142 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR                       (0x2 << 12)
 143 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB                       (0x3 << 12)
 144 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG                       (0x4 << 12)
 145 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR                       (0x5 << 12)
 146 #define LCDIF_CTRL2_READ_PACK_DIR                               (1 << 10)
 147 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT              (1 << 9)
 148 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT                       (1 << 8)
 149 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK          (0x7 << 4)
 150 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET        4
 151 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK                     (0x7 << 1)
 152 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET                   1
 153
 154 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK                       (0xffff << 16)
 155 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET                     16
 156 #define LCDIF_TRANSFER_COUNT_V_COUNT(n)                         (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \
 157                                                 LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
 158 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK                       (0xffff << 0)
 159 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET                     0
 160 #define LCDIF_TRANSFER_COUNT_H_COUNT(n)                         (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \
 161                                                 LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
 162
 163 #define LCDIF_CUR_BUF_ADDR_MASK                                 0xffffffff
 164 #define LCDIF_CUR_BUF_ADDR_OFFSET                               0
 165
 166 #define LCDIF_NEXT_BUF_ADDR_MASK                                0xffffffff
 167 #define LCDIF_NEXT_BUF_ADDR_OFFSET                              0
 168
 169 #define LCDIF_TIMING_CMD_HOLD_MASK                              (0xff << 24)
 170 #define LCDIF_TIMING_CMD_HOLD_OFFSET                            24
 171 #define LCDIF_TIMING_CMD_SETUP_MASK                             (0xff << 16)
 172 #define LCDIF_TIMING_CMD_SETUP_OFFSET                           16
 173 #define LCDIF_TIMING_DATA_HOLD_MASK                             (0xff << 8)
 174 #define LCDIF_TIMING_DATA_HOLD_OFFSET                           8
 175 #define LCDIF_TIMING_DATA_SETUP_MASK                            (0xff << 0)
 176 #define LCDIF_TIMING_DATA_SETUP_OFFSET                          0
 177
 178 #define LCDIF_VDCTRL0_VSYNC_OEB                                 (1 << 29)
 179 #define LCDIF_VDCTRL0_ENABLE_PRESENT                            (1 << 28)
 180 #define LCDIF_VDCTRL0_VSYNC_POL                                 (1 << 27)
 181 #define LCDIF_VDCTRL0_HSYNC_POL                                 (1 << 26)
 182 #define LCDIF_VDCTRL0_DOTCLK_POL                                (1 << 25)
 183 #define LCDIF_VDCTRL0_ENABLE_POL                                (1 << 24)
 184 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT                         (1 << 21)
 185 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT                    (1 << 20)
 186 #define LCDIF_VDCTRL0_HALF_LINE                                 (1 << 19)
 187 #define LCDIF_VDCTRL0_HALF_LINE_MODE                            (1 << 18)
 188 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK                    0x3ffff
 189 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET                  0
 190 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n)                      (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \
 191                                                 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
 192
 193 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK                         0xffffffff
 194 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET                       0
 195 #define LCDIF_VDCTRL1_VSYNC_PERIOD(n)                           (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
 196                                                 LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
 197
 198 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0x3fff << 18)
 199 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  18
 200 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n)                      (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \
 201                                                 LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
 202 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK                         0x3ffff
 203 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET                       0
 204 #define LCDIF_VDCTRL2_HSYNC_PERIOD(n)                           (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \
 205                                                 LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
 206
 207 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS                          (1 << 29)
 208 #define LCDIF_VDCTRL3_VSYNC_ONLY                                (1 << 28)
 209 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK                  (0xfff << 16)
 210 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET                16
 211 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n)                    (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \
 212                                                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
 213 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK                    (0xffff << 0)
 214 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET                  0
 215 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n)                      (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \
 216                                                 LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
 217
 218 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK                       (0x7 << 29)
 219 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET                     29
 220 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n)                         (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \
 221                                                 LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
 222 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON                           (1 << 18)
 223 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK              0x3ffff
 224 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET            0
 225 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n)                (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \
 226                                                         LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
 227
 228 #endif /* __MX6_REGS_LCDIF_H__ */