arch/arm/include/asm/arch-mxs/regs-lcdif.h

   1 /*
   2  * Freescale i.MX28 LCDIF Register Definitions
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Based on code from LTIB:
   8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #ifndef __MX28_REGS_LCDIF_H__
  27 #define __MX28_REGS_LCDIF_H__
  28
  29 #include <asm/imx-common/regs-common.h>
  30
  31 #ifndef __ASSEMBLY__
  32 struct mxs_lcdif_regs {
  33         mxs_reg_32(hw_lcdif_ctrl)               /* 0x00 */
  34         mxs_reg_32(hw_lcdif_ctrl1)              /* 0x10 */
  35 #if defined(CONFIG_MX28)
  36         mxs_reg_32(hw_lcdif_ctrl2)              /* 0x20 */
  37 #endif
  38         mxs_reg_32(hw_lcdif_transfer_count)     /* 0x20/0x30 */
  39         mxs_reg_32(hw_lcdif_cur_buf)            /* 0x30/0x40 */
  40         mxs_reg_32(hw_lcdif_next_buf)           /* 0x40/0x50 */
  41
  42 #if defined(CONFIG_MX23)
  43         uint32_t        reserved1[4];
  44 #endif
  45
  46         mxs_reg_32(hw_lcdif_timing)             /* 0x60 */
  47         mxs_reg_32(hw_lcdif_vdctrl0)            /* 0x70 */
  48         mxs_reg_32(hw_lcdif_vdctrl1)            /* 0x80 */
  49         mxs_reg_32(hw_lcdif_vdctrl2)            /* 0x90 */
  50         mxs_reg_32(hw_lcdif_vdctrl3)            /* 0xa0 */
  51         mxs_reg_32(hw_lcdif_vdctrl4)            /* 0xb0 */
  52         mxs_reg_32(hw_lcdif_dvictrl0)           /* 0xc0 */
  53         mxs_reg_32(hw_lcdif_dvictrl1)           /* 0xd0 */
  54         mxs_reg_32(hw_lcdif_dvictrl2)           /* 0xe0 */
  55         mxs_reg_32(hw_lcdif_dvictrl3)           /* 0xf0 */
  56         mxs_reg_32(hw_lcdif_dvictrl4)           /* 0x100 */
  57         mxs_reg_32(hw_lcdif_csc_coeffctrl0)     /* 0x110 */
  58         mxs_reg_32(hw_lcdif_csc_coeffctrl1)     /* 0x120 */
  59         mxs_reg_32(hw_lcdif_csc_coeffctrl2)     /* 0x130 */
  60         mxs_reg_32(hw_lcdif_csc_coeffctrl3)     /* 0x140 */
  61         mxs_reg_32(hw_lcdif_csc_coeffctrl4)     /* 0x150 */
  62         mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
  63         mxs_reg_32(hw_lcdif_csc_limit)          /* 0x170 */
  64
  65 #if defined(CONFIG_MX23)
  66         uint32_t        reserved2[12];
  67 #endif
  68         mxs_reg_32(hw_lcdif_data)               /* 0x1b0/0x180 */
  69         mxs_reg_32(hw_lcdif_bm_error_stat)      /* 0x1c0/0x190 */
  70 #if defined(CONFIG_MX28)
  71         mxs_reg_32(hw_lcdif_crc_stat)           /* 0x1a0 */
  72 #endif
  73         mxs_reg_32(hw_lcdif_lcdif_stat)         /* 0x1d0/0x1b0 */
  74         mxs_reg_32(hw_lcdif_version)            /* 0x1e0/0x1c0 */
  75         mxs_reg_32(hw_lcdif_debug0)             /* 0x1f0/0x1d0 */
  76         mxs_reg_32(hw_lcdif_debug1)             /* 0x200/0x1e0 */
  77         mxs_reg_32(hw_lcdif_debug2)             /* 0x1f0 */
  78 };
  79 #endif
  80
  81 #define LCDIF_CTRL_SFTRST                                       (1 << 31)
  82 #define LCDIF_CTRL_CLKGATE                                      (1 << 30)
  83 #define LCDIF_CTRL_YCBCR422_INPUT                               (1 << 29)
  84 #define LCDIF_CTRL_READ_WRITEB                                  (1 << 28)
  85 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                          (1 << 27)
  86 #define LCDIF_CTRL_DATA_SHIFT_DIR                               (1 << 26)
  87 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK                          (0x1f << 21)
  88 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET                        21
  89 #define LCDIF_CTRL_DVI_MODE                                     (1 << 20)
  90 #define LCDIF_CTRL_BYPASS_COUNT                                 (1 << 19)
  91 #define LCDIF_CTRL_VSYNC_MODE                                   (1 << 18)
  92 #define LCDIF_CTRL_DOTCLK_MODE                                  (1 << 17)
  93 #define LCDIF_CTRL_DATA_SELECT                                  (1 << 16)
  94 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK                      (0x3 << 14)
  95 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET                    14
  96 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK                        (0x3 << 12)
  97 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET                      12
  98 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK                       (0x3 << 10)
  99 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET                     10
 100 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT                      (0 << 10)
 101 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT                       (1 << 10)
 102 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT                      (2 << 10)
 103 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT                      (3 << 10)
 104 #define LCDIF_CTRL_WORD_LENGTH_MASK                             (0x3 << 8)
 105 #define LCDIF_CTRL_WORD_LENGTH_OFFSET                           8
 106 #define LCDIF_CTRL_WORD_LENGTH_16BIT                            (0 << 8)
 107 #define LCDIF_CTRL_WORD_LENGTH_8BIT                             (1 << 8)
 108 #define LCDIF_CTRL_WORD_LENGTH_18BIT                            (2 << 8)
 109 #define LCDIF_CTRL_WORD_LENGTH_24BIT                            (3 << 8)
 110 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC                          (1 << 7)
 111 #define LCDIF_CTRL_LCDIF_MASTER                                 (1 << 5)
 112 #define LCDIF_CTRL_DATA_FORMAT_16_BIT                           (1 << 3)
 113 #define LCDIF_CTRL_DATA_FORMAT_18_BIT                           (1 << 2)
 114 #define LCDIF_CTRL_DATA_FORMAT_24_BIT                           (1 << 1)
 115 #define LCDIF_CTRL_RUN                                          (1 << 0)
 116
 117 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB                         (1 << 27)
 118 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN                             (1 << 26)
 119 #define LCDIF_CTRL1_BM_ERROR_IRQ                                (1 << 25)
 120 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                        (1 << 24)
 121 #define LCDIF_CTRL1_INTERLACE_FIELDS                            (1 << 23)
 122 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD           (1 << 22)
 123 #define LCDIF_CTRL1_FIFO_CLEAR                                  (1 << 21)
 124 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS                     (1 << 20)
 125 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK                    (0xf << 16)
 126 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET                  16
 127 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN                             (1 << 15)
 128 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN                            (1 << 14)
 129 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                       (1 << 13)
 130 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                           (1 << 12)
 131 #define LCDIF_CTRL1_OVERFLOW_IRQ                                (1 << 11)
 132 #define LCDIF_CTRL1_UNDERFLOW_IRQ                               (1 << 10)
 133 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                          (1 << 9)
 134 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ                              (1 << 8)
 135 #define LCDIF_CTRL1_BUSY_ENABLE                                 (1 << 2)
 136 #define LCDIF_CTRL1_MODE86                                      (1 << 1)
 137 #define LCDIF_CTRL1_RESET                                       (1 << 0)
 138
 139 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK                       (0x7 << 21)
 140 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET                     21
 141 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1                      (0x0 << 21)
 142 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2                      (0x1 << 21)
 143 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4                      (0x2 << 21)
 144 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8                      (0x3 << 21)
 145 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16                     (0x4 << 21)
 146 #define LCDIF_CTRL2_BURST_LEN_8                                 (1 << 20)
 147 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK                       (0x7 << 16)
 148 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET                     16
 149 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB                        (0x0 << 16)
 150 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG                        (0x1 << 16)
 151 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR                        (0x2 << 16)
 152 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB                        (0x3 << 16)
 153 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG                        (0x4 << 16)
 154 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR                        (0x5 << 16)
 155 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK                      (0x7 << 12)
 156 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET                    12
 157 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB                       (0x0 << 12)
 158 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG                       (0x1 << 12)
 159 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR                       (0x2 << 12)
 160 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB                       (0x3 << 12)
 161 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG                       (0x4 << 12)
 162 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR                       (0x5 << 12)
 163 #define LCDIF_CTRL2_READ_PACK_DIR                               (1 << 10)
 164 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT              (1 << 9)
 165 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT                       (1 << 8)
 166 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK          (0x7 << 4)
 167 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET        4
 168 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK                     (0x7 << 1)
 169 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET                   1
 170
 171 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK                       (0xffff << 16)
 172 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET                     16
 173 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK                       (0xffff << 0)
 174 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET                     0
 175
 176 #define LCDIF_CUR_BUF_ADDR_MASK                                 0xffffffff
 177 #define LCDIF_CUR_BUF_ADDR_OFFSET                               0
 178
 179 #define LCDIF_NEXT_BUF_ADDR_MASK                                0xffffffff
 180 #define LCDIF_NEXT_BUF_ADDR_OFFSET                              0
 181
 182 #define LCDIF_TIMING_CMD_HOLD_MASK                              (0xff << 24)
 183 #define LCDIF_TIMING_CMD_HOLD_OFFSET                            24
 184 #define LCDIF_TIMING_CMD_SETUP_MASK                             (0xff << 16)
 185 #define LCDIF_TIMING_CMD_SETUP_OFFSET                           16
 186 #define LCDIF_TIMING_DATA_HOLD_MASK                             (0xff << 8)
 187 #define LCDIF_TIMING_DATA_HOLD_OFFSET                           8
 188 #define LCDIF_TIMING_DATA_SETUP_MASK                            (0xff << 0)
 189 #define LCDIF_TIMING_DATA_SETUP_OFFSET                          0
 190
 191 #define LCDIF_VDCTRL0_VSYNC_OEB                                 (1 << 29)
 192 #define LCDIF_VDCTRL0_ENABLE_PRESENT                            (1 << 28)
 193 #define LCDIF_VDCTRL0_VSYNC_POL                                 (1 << 27)
 194 #define LCDIF_VDCTRL0_HSYNC_POL                                 (1 << 26)
 195 #define LCDIF_VDCTRL0_DOTCLK_POL                                (1 << 25)
 196 #define LCDIF_VDCTRL0_ENABLE_POL                                (1 << 24)
 197 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT                         (1 << 21)
 198 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT                    (1 << 20)
 199 #define LCDIF_VDCTRL0_HALF_LINE                                 (1 << 19)
 200 #define LCDIF_VDCTRL0_HALF_LINE_MODE                            (1 << 18)
 201 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK                    0x3ffff
 202 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET                  0
 203
 204 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK                         0xffffffff
 205 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET                       0
 206
 207 #if defined(CONFIG_MX23)
 208 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0xff << 24)
 209 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  24
 210 #elif defined(CONFIG_MX28)
 211 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0x3fff << 18)
 212 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  18
 213 #endif
 214 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK                         0x3ffff
 215 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET                       0
 216
 217 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS                          (1 << 29)
 218 #define LCDIF_VDCTRL3_VSYNC_ONLY                                (1 << 28)
 219 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK                  (0xfff << 16)
 220 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET                16
 221 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK                    (0xffff << 0)
 222 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET                  0
 223
 224 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK                       (0x7 << 29)
 225 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET                     29
 226 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON                           (1 << 18)
 227 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK              0x3ffff
 228 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET            0
 229
 230 #endif /* __MX28_REGS_LCDIF_H__ */