arch/arm/include/asm/arch-omap4/cpu.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _CPU_H
   9 #define _CPU_H
  10
  11 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  12 #include <asm/types.h>
  13 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  14
  15 #ifndef __KERNEL_STRICT_NAMES
  16 #ifndef __ASSEMBLY__
  17 struct gpmc_cs {
  18         u32 config1;            /* 0x00 */
  19         u32 config2;            /* 0x04 */
  20         u32 config3;            /* 0x08 */
  21         u32 config4;            /* 0x0C */
  22         u32 config5;            /* 0x10 */
  23         u32 config6;            /* 0x14 */
  24         u32 config7;            /* 0x18 */
  25         u32 nand_cmd;           /* 0x1C */
  26         u32 nand_adr;           /* 0x20 */
  27         u32 nand_dat;           /* 0x24 */
  28         u8 res[8];              /* blow up to 0x30 byte */
  29 };
  30
  31 struct gpmc {
  32         u8 res1[0x10];
  33         u32 sysconfig;          /* 0x10 */
  34         u8 res2[0x4];
  35         u32 irqstatus;          /* 0x18 */
  36         u32 irqenable;          /* 0x1C */
  37         u8 res3[0x20];
  38         u32 timeout_control;    /* 0x40 */
  39         u8 res4[0xC];
  40         u32 config;             /* 0x50 */
  41         u32 status;             /* 0x54 */
  42         u8 res5[0x8];   /* 0x58 */
  43         struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
  44         u8 res6[0x14];          /* 0x1E0 */
  45         u32 ecc_config;         /* 0x1F4 */
  46         u32 ecc_control;        /* 0x1F8 */
  47         u32 ecc_size_config;    /* 0x1FC */
  48         u32 ecc1_result;        /* 0x200 */
  49         u32 ecc2_result;        /* 0x204 */
  50         u32 ecc3_result;        /* 0x208 */
  51         u32 ecc4_result;        /* 0x20C */
  52         u32 ecc5_result;        /* 0x210 */
  53         u32 ecc6_result;        /* 0x214 */
  54         u32 ecc7_result;        /* 0x218 */
  55         u32 ecc8_result;        /* 0x21C */
  56         u32 ecc9_result;        /* 0x220 */
  57 };
  58
  59 /* Used for board specific gpmc initialization */
  60 extern struct gpmc *gpmc_cfg;
  61
  62 struct gptimer {
  63         u32 tidr;               /* 0x00 r */
  64         u8 res[0xc];
  65         u32 tiocp_cfg;          /* 0x10 rw */
  66         u32 tistat;             /* 0x14 r */
  67         u32 tisr;               /* 0x18 rw */
  68         u32 tier;               /* 0x1c rw */
  69         u32 twer;               /* 0x20 rw */
  70         u32 tclr;               /* 0x24 rw */
  71         u32 tcrr;               /* 0x28 rw */
  72         u32 tldr;               /* 0x2c rw */
  73         u32 ttgr;               /* 0x30 rw */
  74         u32 twpc;               /* 0x34 r */
  75         u32 tmar;               /* 0x38 rw */
  76         u32 tcar1;              /* 0x3c r */
  77         u32 tcicr;              /* 0x40 rw */
  78         u32 tcar2;              /* 0x44 r */
  79 };
  80 #endif /* __ASSEMBLY__ */
  81 #endif /* __KERNEL_STRICT_NAMES */
  82
  83 /* enable sys_clk NO-prescale /1 */
  84 #define GPT_EN                  ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
  85
  86 /* Watchdog */
  87 #ifndef __KERNEL_STRICT_NAMES
  88 #ifndef __ASSEMBLY__
  89 struct watchdog {
  90         u8 res1[0x34];
  91         u32 wwps;               /* 0x34 r */
  92         u8 res2[0x10];
  93         u32 wspr;               /* 0x48 rw */
  94 };
  95 #endif /* __ASSEMBLY__ */
  96 #endif /* __KERNEL_STRICT_NAMES */
  97
  98 #define WD_UNLOCK1              0xAAAA
  99 #define WD_UNLOCK2              0x5555
 100
 101 #define TCLR_ST                 (0x1 << 0)
 102 #define TCLR_AR                 (0x1 << 1)
 103 #define TCLR_PRE                (0x1 << 5)
 104
 105 /* GPMC BASE */
 106 #define GPMC_BASE               (OMAP44XX_GPMC_BASE)
 107
 108 /* I2C base */
 109 #define I2C_BASE1               (OMAP44XX_L4_PER_BASE + 0x70000)
 110 #define I2C_BASE2               (OMAP44XX_L4_PER_BASE + 0x72000)
 111 #define I2C_BASE3               (OMAP44XX_L4_PER_BASE + 0x60000)
 112 #define I2C_BASE4               (OMAP44XX_L4_PER_BASE + 0x350000)
 113
 114 /* MUSB base */
 115 #define MUSB_BASE               (OMAP44XX_L4_CORE_BASE + 0xAB000)
 116
 117 /* OMAP4 GPIO registers */
 118 #define OMAP_GPIO_REVISION              0x0000
 119 #define OMAP_GPIO_SYSCONFIG             0x0010
 120 #define OMAP_GPIO_SYSSTATUS             0x0114
 121 #define OMAP_GPIO_IRQSTATUS1            0x0118
 122 #define OMAP_GPIO_IRQSTATUS2            0x0128
 123 #define OMAP_GPIO_IRQENABLE2            0x012c
 124 #define OMAP_GPIO_IRQENABLE1            0x011c
 125 #define OMAP_GPIO_WAKE_EN               0x0120
 126 #define OMAP_GPIO_CTRL                  0x0130
 127 #define OMAP_GPIO_OE                    0x0134
 128 #define OMAP_GPIO_DATAIN                0x0138
 129 #define OMAP_GPIO_DATAOUT               0x013c
 130 #define OMAP_GPIO_LEVELDETECT0          0x0140
 131 #define OMAP_GPIO_LEVELDETECT1          0x0144
 132 #define OMAP_GPIO_RISINGDETECT          0x0148
 133 #define OMAP_GPIO_FALLINGDETECT         0x014c
 134 #define OMAP_GPIO_DEBOUNCE_EN           0x0150
 135 #define OMAP_GPIO_DEBOUNCE_VAL          0x0154
 136 #define OMAP_GPIO_CLEARIRQENABLE1       0x0160
 137 #define OMAP_GPIO_SETIRQENABLE1         0x0164
 138 #define OMAP_GPIO_CLEARWKUENA           0x0180
 139 #define OMAP_GPIO_SETWKUENA             0x0184
 140 #define OMAP_GPIO_CLEARDATAOUT          0x0190
 141 #define OMAP_GPIO_SETDATAOUT            0x0194
 142
 143 /*
 144  * PRCM
 145  */
 146
 147 /* PRM */
 148 #define PRM_BASE                0x4A306000
 149 #define PRM_DEVICE_BASE         (PRM_BASE + 0x1B00)
 150
 151 #define PRM_RSTCTRL             PRM_DEVICE_BASE
 152 #define PRM_RSTCTRL_RESET       0x01
 153 #define PRM_RSTST               (PRM_DEVICE_BASE + 0x4)
 154 #define PRM_RSTST_WARM_RESET_MASK       0x07EA
 155
 156 #endif /* _CPU_H */