arch/arm/include/asm/arch-tegra124/usb.h

   1 /*
   2  * (C) Copyright 2013
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _TEGRA124_USB_H_
   9 #define _TEGRA124_USB_H_
  10
  11
  12 /* USB Controller (USBx_CONTROLLER_) regs */
  13 struct usb_ctlr {
  14         /* 0x000 */
  15         uint id;
  16         uint reserved0;
  17         uint host;
  18         uint device;
  19
  20         /* 0x010 */
  21         uint txbuf;
  22         uint rxbuf;
  23         uint reserved1[2];
  24
  25         /* 0x020 */
  26         uint reserved2[56];
  27
  28         /* 0x100 */
  29         u16 cap_length;
  30         u16 hci_version;
  31         uint hcs_params;
  32         uint hcc_params;
  33         uint reserved3[5];
  34
  35         /* 0x120 */
  36         uint dci_version;
  37         uint dcc_params;
  38         uint reserved4[2];
  39
  40         /* 0x130 */
  41         uint usb_cmd;
  42         uint usb_sts;
  43         uint usb_intr;
  44         uint frindex;
  45
  46         /* 0x140 */
  47         uint reserved5;
  48         uint periodic_list_base;
  49         uint async_list_addr;
  50         uint reserved5_1;
  51
  52         /* 0x150 */
  53         uint burst_size;
  54         uint tx_fill_tuning;
  55         uint reserved6;
  56         uint icusb_ctrl;
  57
  58         /* 0x160 */
  59         uint ulpi_viewport;
  60         uint reserved7;
  61         uint reserved7_0;
  62         uint reserved7_1;
  63
  64         /* 0x170 */
  65         uint reserved;
  66         uint port_sc1;
  67         uint reserved8[6];
  68
  69         /* 0x190 */
  70         uint reserved9[8];
  71
  72         /* 0x1b0 */
  73         uint reserved10;
  74         uint hostpc1_devlc;
  75         uint reserved10_1[2];
  76
  77         /* 0x1c0 */
  78         uint reserved10_2[4];
  79
  80         /* 0x1d0 */
  81         uint reserved10_3[4];
  82
  83         /* 0x1e0 */
  84         uint reserved10_4[4];
  85
  86         /* 0x1f0 */
  87         uint reserved10_5;
  88         uint otgsc;
  89         uint usb_mode;
  90         uint reserved10_6;
  91
  92         /* 0x200 */
  93         uint endpt_nak;
  94         uint endpt_nak_enable;
  95         uint endpt_setup_stat;
  96         uint reserved11_1[0x7D];
  97
  98         /* 0x400 */
  99         uint susp_ctrl;
 100         uint phy_vbus_sensors;
 101         uint phy_vbus_wakeup_id;
 102         uint phy_alt_vbus_sys;
 103
 104         /* 0x410 */
 105         uint usb1_legacy_ctrl;
 106         uint reserved12[3];
 107
 108         /* 0x420 */
 109         uint reserved13[56];
 110
 111         /* 0x500 */
 112         uint reserved14[64 * 3];
 113
 114         /* 0x800 */
 115         uint utmip_pll_cfg0;
 116         uint utmip_pll_cfg1;
 117         uint utmip_xcvr_cfg0;
 118         uint utmip_bias_cfg0;
 119
 120         /* 0x810 */
 121         uint utmip_hsrx_cfg0;
 122         uint utmip_hsrx_cfg1;
 123         uint utmip_fslsrx_cfg0;
 124         uint utmip_fslsrx_cfg1;
 125
 126         /* 0x820 */
 127         uint utmip_tx_cfg0;
 128         uint utmip_misc_cfg0;
 129         uint utmip_misc_cfg1;
 130         uint utmip_debounce_cfg0;
 131
 132         /* 0x830 */
 133         uint utmip_bat_chrg_cfg0;
 134         uint utmip_spare_cfg0;
 135         uint utmip_xcvr_cfg1;
 136         uint utmip_bias_cfg1;
 137 };
 138
 139 /* USB1_LEGACY_CTRL */
 140 #define USB1_NO_LEGACY_MODE             1
 141
 142 #define VBUS_SENSE_CTL_SHIFT                    1
 143 #define VBUS_SENSE_CTL_MASK                     (3 << VBUS_SENSE_CTL_SHIFT)
 144 #define VBUS_SENSE_CTL_VBUS_WAKEUP              0
 145 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP       1
 146 #define VBUS_SENSE_CTL_AB_SESS_VLD              2
 147 #define VBUS_SENSE_CTL_A_SESS_VLD               3
 148
 149 /* USBx_IF_USB_SUSP_CTRL_0 */
 150 #define UTMIP_PHY_ENB                           (1 << 12)
 151 #define UTMIP_RESET                             (1 << 11)
 152 #define USB_PHY_CLK_VALID                       (1 << 7)
 153 #define USB_SUSP_CLR                            (1 << 5)
 154
 155 /* USBx_UTMIP_MISC_CFG0 */
 156 #define UTMIP_SUSPEND_EXIT_ON_EDGE              (1 << 22)
 157
 158 /* USBx_UTMIP_MISC_CFG1 */
 159 #define UTMIP_PHY_XTAL_CLOCKEN                  (1 << 30)
 160
 161 /* Moved to Clock and Reset register space */
 162 #define UTMIP_PLLU_STABLE_COUNT_SHIFT           6
 163 #define UTMIP_PLLU_STABLE_COUNT_MASK            \
 164                                 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
 165 /* Moved to Clock and Reset register space */
 166 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT        18
 167 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK         \
 168                                 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
 169
 170 /* USBx_UTMIP_PLL_CFG1_0 */
 171 /* Moved to Clock and Reset register space */
 172 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT       27
 173 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK        \
 174                                 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
 175 #define UTMIP_XTAL_FREQ_COUNT_SHIFT             0
 176 #define UTMIP_XTAL_FREQ_COUNT_MASK              0xfff
 177
 178 /* USBx_UTMIP_BIAS_CFG0_0 */
 179 #define UTMIP_HSDISCON_LEVEL_MSB                (1 << 24)
 180 #define UTMIP_OTGPD                             (1 << 11)
 181 #define UTMIP_BIASPD                            (1 << 10)
 182 #define UTMIP_HSDISCON_LEVEL_SHIFT              2
 183 #define UTMIP_HSDISCON_LEVEL_MASK               \
 184                                 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
 185 #define UTMIP_HSSQUELCH_LEVEL_SHIFT             0
 186 #define UTMIP_HSSQUELCH_LEVEL_MASK              \
 187                                 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
 188
 189 /* USBx_UTMIP_BIAS_CFG1_0 */
 190 #define UTMIP_FORCE_PDTRK_POWERDOWN             1
 191 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT            3
 192 #define UTMIP_BIAS_PDTRK_COUNT_MASK             \
 193                                 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
 194
 195 /* USBx_UTMIP_DEBOUNCE_CFG0_0 */
 196 #define UTMIP_DEBOUNCE_CFG0_SHIFT               0
 197 #define UTMIP_DEBOUNCE_CFG0_MASK                0xffff
 198
 199 /* USBx_UTMIP_TX_CFG0_0 */
 200 #define UTMIP_FS_PREAMBLE_J                     (1 << 19)
 201
 202 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
 203 #define UTMIP_PD_CHRG                           1
 204
 205 /* USBx_UTMIP_SPARE_CFG0_0 */
 206 #define FUSE_SETUP_SEL                          (1 << 3)
 207
 208 /* USBx_UTMIP_HSRX_CFG0_0 */
 209 #define UTMIP_IDLE_WAIT_SHIFT                   15
 210 #define UTMIP_IDLE_WAIT_MASK                    (0x1f << UTMIP_IDLE_WAIT_SHIFT)
 211 #define UTMIP_ELASTIC_LIMIT_SHIFT               10
 212 #define UTMIP_ELASTIC_LIMIT_MASK                \
 213                                 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
 214
 215 /* USBx_UTMIP_HSRX_CFG0_1 */
 216 #define UTMIP_HS_SYNC_START_DLY_SHIFT           1
 217 #define UTMIP_HS_SYNC_START_DLY_MASK            \
 218                                 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
 219
 220 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 221 #define IC_ENB1                                 (1 << 3)
 222
 223 /* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
 224 #define PTS1_SHIFT                              31
 225 #define PTS1_MASK                               (1 << PTS1_SHIFT)
 226 #define STS1                                    (1 << 30)
 227
 228 /* USB2D_HOSTPC1_DEVLC_0 */
 229 #define PTS_SHIFT                               29
 230 #define PTS_MASK                                (0x7U << PTS_SHIFT)
 231 #define PTS_UTMI        0
 232 #define PTS_RESERVED    1
 233 #define PTS_ULPI        2
 234 #define PTS_ICUSB_SER   3
 235 #define PTS_HSIC        4
 236
 237 #define STS                                     (1 << 28)
 238
 239 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
 240 #define WKOC                            (1 << 22)
 241 #define WKDS                            (1 << 21)
 242 #define WKCN                            (1 << 20)
 243
 244 /* USBx_UTMIP_XCVR_CFG0_0 */
 245 #define UTMIP_FORCE_PD_POWERDOWN                (1 << 14)
 246 #define UTMIP_FORCE_PD2_POWERDOWN               (1 << 16)
 247 #define UTMIP_FORCE_PDZI_POWERDOWN              (1 << 18)
 248 #define UTMIP_XCVR_LSBIAS_SE                    (1 << 21)
 249 #define UTMIP_XCVR_HSSLEW_MSB_SHIFT             25
 250 #define UTMIP_XCVR_HSSLEW_MSB_MASK              \
 251                         (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
 252 #define UTMIP_XCVR_SETUP_MSB_SHIFT      22
 253 #define UTMIP_XCVR_SETUP_MSB_MASK       (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
 254 #define UTMIP_XCVR_SETUP_SHIFT          0
 255 #define UTMIP_XCVR_SETUP_MASK           (0xf << UTMIP_XCVR_SETUP_SHIFT)
 256
 257 /* USBx_UTMIP_XCVR_CFG1_0 */
 258 #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT         18
 259 #define UTMIP_XCVR_TERM_RANGE_ADJ_MASK          \
 260                         (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
 261 #define UTMIP_FORCE_PDDISC_POWERDOWN            (1 << 0)
 262 #define UTMIP_FORCE_PDCHRP_POWERDOWN            (1 << 2)
 263 #define UTMIP_FORCE_PDDR_POWERDOWN              (1 << 4)
 264
 265 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
 266 #define VBUS_VLD_STS                    (1 << 26)
 267
 268 #endif  /* _TEGRA124_USB_H_ */