0dbe81b59c64c1d9c0b1b0a6077b569e68e7e28f
[karo-tx-uboot.git] / arch / arm / include / asm / omap_common.h
1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  *
5  * Aneesh V <aneesh@ti.com>
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 #ifndef _OMAP_COMMON_H_
26 #define _OMAP_COMMON_H_
27
28 #ifndef __ASSEMBLY__
29
30 #include <common.h>
31
32 #define NUM_SYS_CLKS    7
33
34 struct prcm_regs {
35         /* cm1.ckgen */
36         u32 cm_clksel_core;
37         u32 cm_clksel_abe;
38         u32 cm_dll_ctrl;
39         u32 cm_clkmode_dpll_core;
40         u32 cm_idlest_dpll_core;
41         u32 cm_autoidle_dpll_core;
42         u32 cm_clksel_dpll_core;
43         u32 cm_div_m2_dpll_core;
44         u32 cm_div_m3_dpll_core;
45         u32 cm_div_h11_dpll_core;
46         u32 cm_div_h12_dpll_core;
47         u32 cm_div_h13_dpll_core;
48         u32 cm_div_h14_dpll_core;
49         u32 cm_div_h21_dpll_core;
50         u32 cm_div_h24_dpll_core;
51         u32 cm_ssc_deltamstep_dpll_core;
52         u32 cm_ssc_modfreqdiv_dpll_core;
53         u32 cm_emu_override_dpll_core;
54         u32 cm_div_h22_dpllcore;
55         u32 cm_div_h23_dpll_core;
56         u32 cm_clkmode_dpll_mpu;
57         u32 cm_idlest_dpll_mpu;
58         u32 cm_autoidle_dpll_mpu;
59         u32 cm_clksel_dpll_mpu;
60         u32 cm_div_m2_dpll_mpu;
61         u32 cm_ssc_deltamstep_dpll_mpu;
62         u32 cm_ssc_modfreqdiv_dpll_mpu;
63         u32 cm_bypclk_dpll_mpu;
64         u32 cm_clkmode_dpll_iva;
65         u32 cm_idlest_dpll_iva;
66         u32 cm_autoidle_dpll_iva;
67         u32 cm_clksel_dpll_iva;
68         u32 cm_div_h11_dpll_iva;
69         u32 cm_div_h12_dpll_iva;
70         u32 cm_ssc_deltamstep_dpll_iva;
71         u32 cm_ssc_modfreqdiv_dpll_iva;
72         u32 cm_bypclk_dpll_iva;
73         u32 cm_clkmode_dpll_abe;
74         u32 cm_idlest_dpll_abe;
75         u32 cm_autoidle_dpll_abe;
76         u32 cm_clksel_dpll_abe;
77         u32 cm_div_m2_dpll_abe;
78         u32 cm_div_m3_dpll_abe;
79         u32 cm_ssc_deltamstep_dpll_abe;
80         u32 cm_ssc_modfreqdiv_dpll_abe;
81         u32 cm_clkmode_dpll_ddrphy;
82         u32 cm_idlest_dpll_ddrphy;
83         u32 cm_autoidle_dpll_ddrphy;
84         u32 cm_clksel_dpll_ddrphy;
85         u32 cm_div_m2_dpll_ddrphy;
86         u32 cm_div_h11_dpll_ddrphy;
87         u32 cm_div_h12_dpll_ddrphy;
88         u32 cm_div_h13_dpll_ddrphy;
89         u32 cm_ssc_deltamstep_dpll_ddrphy;
90         u32 cm_clkmode_dpll_dsp;
91         u32 cm_shadow_freq_config1;
92         u32 cm_mpu_mpu_clkctrl;
93
94         /* cm1.dsp */
95         u32 cm_dsp_clkstctrl;
96         u32 cm_dsp_dsp_clkctrl;
97
98         /* cm1.abe */
99         u32 cm1_abe_clkstctrl;
100         u32 cm1_abe_l4abe_clkctrl;
101         u32 cm1_abe_aess_clkctrl;
102         u32 cm1_abe_pdm_clkctrl;
103         u32 cm1_abe_dmic_clkctrl;
104         u32 cm1_abe_mcasp_clkctrl;
105         u32 cm1_abe_mcbsp1_clkctrl;
106         u32 cm1_abe_mcbsp2_clkctrl;
107         u32 cm1_abe_mcbsp3_clkctrl;
108         u32 cm1_abe_slimbus_clkctrl;
109         u32 cm1_abe_timer5_clkctrl;
110         u32 cm1_abe_timer6_clkctrl;
111         u32 cm1_abe_timer7_clkctrl;
112         u32 cm1_abe_timer8_clkctrl;
113         u32 cm1_abe_wdt3_clkctrl;
114
115         /* cm2.ckgen */
116         u32 cm_clksel_mpu_m3_iss_root;
117         u32 cm_clksel_usb_60mhz;
118         u32 cm_scale_fclk;
119         u32 cm_core_dvfs_perf1;
120         u32 cm_core_dvfs_perf2;
121         u32 cm_core_dvfs_perf3;
122         u32 cm_core_dvfs_perf4;
123         u32 cm_core_dvfs_current;
124         u32 cm_iva_dvfs_perf_tesla;
125         u32 cm_iva_dvfs_perf_ivahd;
126         u32 cm_iva_dvfs_perf_abe;
127         u32 cm_iva_dvfs_current;
128         u32 cm_clkmode_dpll_per;
129         u32 cm_idlest_dpll_per;
130         u32 cm_autoidle_dpll_per;
131         u32 cm_clksel_dpll_per;
132         u32 cm_div_m2_dpll_per;
133         u32 cm_div_m3_dpll_per;
134         u32 cm_div_h11_dpll_per;
135         u32 cm_div_h12_dpll_per;
136         u32 cm_div_h13_dpll_per;
137         u32 cm_div_h14_dpll_per;
138         u32 cm_ssc_deltamstep_dpll_per;
139         u32 cm_ssc_modfreqdiv_dpll_per;
140         u32 cm_emu_override_dpll_per;
141         u32 cm_clkmode_dpll_usb;
142         u32 cm_idlest_dpll_usb;
143         u32 cm_autoidle_dpll_usb;
144         u32 cm_clksel_dpll_usb;
145         u32 cm_div_m2_dpll_usb;
146         u32 cm_ssc_deltamstep_dpll_usb;
147         u32 cm_ssc_modfreqdiv_dpll_usb;
148         u32 cm_clkdcoldo_dpll_usb;
149         u32 cm_clkmode_dpll_pcie_ref;
150         u32 cm_clkmode_apll_pcie;
151         u32 cm_idlest_apll_pcie;
152         u32 cm_div_m2_apll_pcie;
153         u32 cm_clkvcoldo_apll_pcie;
154         u32 cm_clkmode_dpll_unipro;
155         u32 cm_idlest_dpll_unipro;
156         u32 cm_autoidle_dpll_unipro;
157         u32 cm_clksel_dpll_unipro;
158         u32 cm_div_m2_dpll_unipro;
159         u32 cm_ssc_deltamstep_dpll_unipro;
160         u32 cm_ssc_modfreqdiv_dpll_unipro;
161
162         /* cm2.core */
163         u32 cm_coreaon_bandgap_clkctrl;
164         u32 cm_coreaon_io_srcomp_clkctrl;
165         u32 cm_l3_1_clkstctrl;
166         u32 cm_l3_1_dynamicdep;
167         u32 cm_l3_1_l3_1_clkctrl;
168         u32 cm_l3_2_clkstctrl;
169         u32 cm_l3_2_dynamicdep;
170         u32 cm_l3_2_l3_2_clkctrl;
171         u32 cm_l3_gpmc_clkctrl;
172         u32 cm_l3_2_ocmc_ram_clkctrl;
173         u32 cm_mpu_m3_clkstctrl;
174         u32 cm_mpu_m3_staticdep;
175         u32 cm_mpu_m3_dynamicdep;
176         u32 cm_mpu_m3_mpu_m3_clkctrl;
177         u32 cm_sdma_clkstctrl;
178         u32 cm_sdma_staticdep;
179         u32 cm_sdma_dynamicdep;
180         u32 cm_sdma_sdma_clkctrl;
181         u32 cm_memif_clkstctrl;
182         u32 cm_memif_dmm_clkctrl;
183         u32 cm_memif_emif_fw_clkctrl;
184         u32 cm_memif_emif_1_clkctrl;
185         u32 cm_memif_emif_2_clkctrl;
186         u32 cm_memif_dll_clkctrl;
187         u32 cm_memif_emif_h1_clkctrl;
188         u32 cm_memif_emif_h2_clkctrl;
189         u32 cm_memif_dll_h_clkctrl;
190         u32 cm_c2c_clkstctrl;
191         u32 cm_c2c_staticdep;
192         u32 cm_c2c_dynamicdep;
193         u32 cm_c2c_sad2d_clkctrl;
194         u32 cm_c2c_modem_icr_clkctrl;
195         u32 cm_c2c_sad2d_fw_clkctrl;
196         u32 cm_l4cfg_clkstctrl;
197         u32 cm_l4cfg_dynamicdep;
198         u32 cm_l4cfg_l4_cfg_clkctrl;
199         u32 cm_l4cfg_hw_sem_clkctrl;
200         u32 cm_l4cfg_mailbox_clkctrl;
201         u32 cm_l4cfg_sar_rom_clkctrl;
202         u32 cm_l3instr_clkstctrl;
203         u32 cm_l3instr_l3_3_clkctrl;
204         u32 cm_l3instr_l3_instr_clkctrl;
205         u32 cm_l3instr_intrconn_wp1_clkctrl;
206
207         /* cm2.ivahd */
208         u32 cm_ivahd_clkstctrl;
209         u32 cm_ivahd_ivahd_clkctrl;
210         u32 cm_ivahd_sl2_clkctrl;
211
212         /* cm2.cam */
213         u32 cm_cam_clkstctrl;
214         u32 cm_cam_iss_clkctrl;
215         u32 cm_cam_fdif_clkctrl;
216         u32 cm_cam_vip1_clkctrl;
217         u32 cm_cam_vip2_clkctrl;
218         u32 cm_cam_vip3_clkctrl;
219         u32 cm_cam_lvdsrx_clkctrl;
220         u32 cm_cam_csi1_clkctrl;
221         u32 cm_cam_csi2_clkctrl;
222
223         /* cm2.dss */
224         u32 cm_dss_clkstctrl;
225         u32 cm_dss_dss_clkctrl;
226
227         /* cm2.sgx */
228         u32 cm_sgx_clkstctrl;
229         u32 cm_sgx_sgx_clkctrl;
230
231         /* cm2.l3init */
232         u32 cm_l3init_clkstctrl;
233
234         /* cm2.l3init */
235         u32 cm_l3init_hsmmc1_clkctrl;
236         u32 cm_l3init_hsmmc2_clkctrl;
237         u32 cm_l3init_hsi_clkctrl;
238         u32 cm_l3init_hsusbhost_clkctrl;
239         u32 cm_l3init_hsusbotg_clkctrl;
240         u32 cm_l3init_hsusbtll_clkctrl;
241         u32 cm_l3init_p1500_clkctrl;
242         u32 cm_l3init_fsusb_clkctrl;
243         u32 cm_l3init_ocp2scp1_clkctrl;
244
245         u32 prm_irqstatus_mpu_2;
246
247         /* cm2.l4per */
248         u32 cm_l4per_clkstctrl;
249         u32 cm_l4per_dynamicdep;
250         u32 cm_l4per_adc_clkctrl;
251         u32 cm_l4per_gptimer10_clkctrl;
252         u32 cm_l4per_gptimer11_clkctrl;
253         u32 cm_l4per_gptimer2_clkctrl;
254         u32 cm_l4per_gptimer3_clkctrl;
255         u32 cm_l4per_gptimer4_clkctrl;
256         u32 cm_l4per_gptimer9_clkctrl;
257         u32 cm_l4per_elm_clkctrl;
258         u32 cm_l4per_gpio2_clkctrl;
259         u32 cm_l4per_gpio3_clkctrl;
260         u32 cm_l4per_gpio4_clkctrl;
261         u32 cm_l4per_gpio5_clkctrl;
262         u32 cm_l4per_gpio6_clkctrl;
263         u32 cm_l4per_hdq1w_clkctrl;
264         u32 cm_l4per_hecc1_clkctrl;
265         u32 cm_l4per_hecc2_clkctrl;
266         u32 cm_l4per_i2c1_clkctrl;
267         u32 cm_l4per_i2c2_clkctrl;
268         u32 cm_l4per_i2c3_clkctrl;
269         u32 cm_l4per_i2c4_clkctrl;
270         u32 cm_l4per_l4per_clkctrl;
271         u32 cm_l4per_mcasp2_clkctrl;
272         u32 cm_l4per_mcasp3_clkctrl;
273         u32 cm_l4per_mgate_clkctrl;
274         u32 cm_l4per_mcspi1_clkctrl;
275         u32 cm_l4per_mcspi2_clkctrl;
276         u32 cm_l4per_mcspi3_clkctrl;
277         u32 cm_l4per_mcspi4_clkctrl;
278         u32 cm_l4per_gpio7_clkctrl;
279         u32 cm_l4per_gpio8_clkctrl;
280         u32 cm_l4per_mmcsd3_clkctrl;
281         u32 cm_l4per_mmcsd4_clkctrl;
282         u32 cm_l4per_msprohg_clkctrl;
283         u32 cm_l4per_slimbus2_clkctrl;
284         u32 cm_l4per_uart1_clkctrl;
285         u32 cm_l4per_uart2_clkctrl;
286         u32 cm_l4per_uart3_clkctrl;
287         u32 cm_l4per_uart4_clkctrl;
288         u32 cm_l4per_mmcsd5_clkctrl;
289         u32 cm_l4per_i2c5_clkctrl;
290         u32 cm_l4per_uart5_clkctrl;
291         u32 cm_l4per_uart6_clkctrl;
292         u32 cm_l4sec_clkstctrl;
293         u32 cm_l4sec_staticdep;
294         u32 cm_l4sec_dynamicdep;
295         u32 cm_l4sec_aes1_clkctrl;
296         u32 cm_l4sec_aes2_clkctrl;
297         u32 cm_l4sec_des3des_clkctrl;
298         u32 cm_l4sec_pkaeip29_clkctrl;
299         u32 cm_l4sec_rng_clkctrl;
300         u32 cm_l4sec_sha2md51_clkctrl;
301         u32 cm_l4sec_cryptodma_clkctrl;
302
303         /* l4 wkup regs */
304         u32 cm_abe_pll_ref_clksel;
305         u32 cm_sys_clksel;
306         u32 cm_abe_pll_sys_clksel;
307         u32 cm_wkup_clkstctrl;
308         u32 cm_wkup_l4wkup_clkctrl;
309         u32 cm_wkup_wdtimer1_clkctrl;
310         u32 cm_wkup_wdtimer2_clkctrl;
311         u32 cm_wkup_gpio1_clkctrl;
312         u32 cm_wkup_gptimer1_clkctrl;
313         u32 cm_wkup_gptimer12_clkctrl;
314         u32 cm_wkup_synctimer_clkctrl;
315         u32 cm_wkup_usim_clkctrl;
316         u32 cm_wkup_sarram_clkctrl;
317         u32 cm_wkup_keyboard_clkctrl;
318         u32 cm_wkup_rtc_clkctrl;
319         u32 cm_wkup_bandgap_clkctrl;
320         u32 cm_wkupaon_scrm_clkctrl;
321         u32 cm_wkupaon_io_srcomp_clkctrl;
322         u32 prm_rstctrl;
323         u32 prm_rstst;
324         u32 prm_rsttime;
325         u32 prm_vc_val_bypass;
326         u32 prm_vc_cfg_i2c_mode;
327         u32 prm_vc_cfg_i2c_clk;
328         u32 prm_sldo_core_setup;
329         u32 prm_sldo_core_ctrl;
330         u32 prm_sldo_mpu_setup;
331         u32 prm_sldo_mpu_ctrl;
332         u32 prm_sldo_mm_setup;
333         u32 prm_sldo_mm_ctrl;
334         u32 prm_abbldo_mpu_setup;
335         u32 prm_abbldo_mpu_ctrl;
336
337         u32 cm_div_m4_dpll_core;
338         u32 cm_div_m5_dpll_core;
339         u32 cm_div_m6_dpll_core;
340         u32 cm_div_m7_dpll_core;
341         u32 cm_div_m4_dpll_iva;
342         u32 cm_div_m5_dpll_iva;
343         u32 cm_div_m4_dpll_ddrphy;
344         u32 cm_div_m5_dpll_ddrphy;
345         u32 cm_div_m6_dpll_ddrphy;
346         u32 cm_div_m4_dpll_per;
347         u32 cm_div_m5_dpll_per;
348         u32 cm_div_m6_dpll_per;
349         u32 cm_div_m7_dpll_per;
350         u32 cm_l3instr_intrconn_wp1_clkct;
351         u32 cm_l3init_usbphy_clkctrl;
352         u32 cm_l4per_mcbsp4_clkctrl;
353         u32 prm_vc_cfg_channel;
354
355         /* SCRM stuff, used by some boards */
356         u32 scrm_auxclk0;
357         u32 scrm_auxclk1;
358 };
359
360 struct omap_sys_ctrl_regs {
361         u32 control_status;
362         u32 control_std_fuse_opp_vdd_mpu_2;
363         u32 control_core_mmr_lock1;
364         u32 control_core_mmr_lock2;
365         u32 control_core_mmr_lock3;
366         u32 control_core_mmr_lock4;
367         u32 control_core_mmr_lock5;
368         u32 control_core_control_io1;
369         u32 control_core_control_io2;
370         u32 control_id_code;
371         u32 control_std_fuse_opp_bgap;
372         u32 control_ldosram_iva_voltage_ctrl;
373         u32 control_ldosram_mpu_voltage_ctrl;
374         u32 control_ldosram_core_voltage_ctrl;
375         u32 control_usbotghs_ctrl;
376         u32 control_padconf_core_base;
377         u32 control_paconf_global;
378         u32 control_paconf_mode;
379         u32 control_smart1io_padconf_0;
380         u32 control_smart1io_padconf_1;
381         u32 control_smart1io_padconf_2;
382         u32 control_smart2io_padconf_0;
383         u32 control_smart2io_padconf_1;
384         u32 control_smart2io_padconf_2;
385         u32 control_smart3io_padconf_0;
386         u32 control_smart3io_padconf_1;
387         u32 control_pbias;
388         u32 control_i2c_0;
389         u32 control_camera_rx;
390         u32 control_hdmi_tx_phy;
391         u32 control_uniportm;
392         u32 control_dsiphy;
393         u32 control_mcbsplp;
394         u32 control_usb2phycore;
395         u32 control_hdmi_1;
396         u32 control_hsi;
397         u32 control_ddr3ch1_0;
398         u32 control_ddr3ch2_0;
399         u32 control_ddrch1_0;
400         u32 control_ddrch1_1;
401         u32 control_ddrch2_0;
402         u32 control_ddrch2_1;
403         u32 control_lpddr2ch1_0;
404         u32 control_lpddr2ch1_1;
405         u32 control_ddrio_0;
406         u32 control_ddrio_1;
407         u32 control_ddrio_2;
408         u32 control_ddr_control_ext_0;
409         u32 control_lpddr2io1_0;
410         u32 control_lpddr2io1_1;
411         u32 control_lpddr2io1_2;
412         u32 control_lpddr2io1_3;
413         u32 control_lpddr2io2_0;
414         u32 control_lpddr2io2_1;
415         u32 control_lpddr2io2_2;
416         u32 control_lpddr2io2_3;
417         u32 control_hyst_1;
418         u32 control_usbb_hsic_control;
419         u32 control_c2c;
420         u32 control_core_control_spare_rw;
421         u32 control_core_control_spare_r;
422         u32 control_core_control_spare_r_c0;
423         u32 control_srcomp_north_side;
424         u32 control_srcomp_south_side;
425         u32 control_srcomp_east_side;
426         u32 control_srcomp_west_side;
427         u32 control_srcomp_code_latch;
428         u32 control_pbiaslite;
429         u32 control_port_emif1_sdram_config;
430         u32 control_port_emif1_lpddr2_nvm_config;
431         u32 control_port_emif2_sdram_config;
432         u32 control_emif1_sdram_config_ext;
433         u32 control_emif2_sdram_config_ext;
434         u32 control_wkup_ldovbb_mpu_voltage_ctrl;
435         u32 control_smart1nopmio_padconf_0;
436         u32 control_smart1nopmio_padconf_1;
437         u32 control_padconf_mode;
438         u32 control_xtal_oscillator;
439         u32 control_i2c_2;
440         u32 control_ckobuffer;
441         u32 control_wkup_control_spare_rw;
442         u32 control_wkup_control_spare_r;
443         u32 control_wkup_control_spare_r_c0;
444         u32 control_srcomp_east_side_wkup;
445         u32 control_efuse_1;
446         u32 control_efuse_2;
447         u32 control_efuse_3;
448         u32 control_efuse_4;
449         u32 control_efuse_5;
450         u32 control_efuse_6;
451         u32 control_efuse_7;
452         u32 control_efuse_8;
453         u32 control_efuse_9;
454         u32 control_efuse_10;
455         u32 control_efuse_11;
456         u32 control_efuse_12;
457         u32 control_efuse_13;
458         u32 control_padconf_wkup_base;
459 };
460
461 struct dpll_params {
462         u32 m;
463         u32 n;
464         s8 m2;
465         s8 m3;
466         s8 m4_h11;
467         s8 m5_h12;
468         s8 m6_h13;
469         s8 m7_h14;
470         s8 h21;
471         s8 h22;
472         s8 h23;
473         s8 h24;
474 };
475
476 struct dpll_regs {
477         u32 cm_clkmode_dpll;
478         u32 cm_idlest_dpll;
479         u32 cm_autoidle_dpll;
480         u32 cm_clksel_dpll;
481         u32 cm_div_m2_dpll;
482         u32 cm_div_m3_dpll;
483         u32 cm_div_m4_h11_dpll;
484         u32 cm_div_m5_h12_dpll;
485         u32 cm_div_m6_h13_dpll;
486         u32 cm_div_m7_h14_dpll;
487         u32 reserved[2];
488         u32 cm_div_h21_dpll;
489         u32 cm_div_h22_dpll;
490         u32 cm_div_h23_dpll;
491         u32 cm_div_h24_dpll;
492 };
493
494 struct dplls {
495         const struct dpll_params *mpu;
496         const struct dpll_params *core;
497         const struct dpll_params *per;
498         const struct dpll_params *abe;
499         const struct dpll_params *iva;
500         const struct dpll_params *usb;
501         const struct dpll_params *ddr;
502 };
503
504 struct pmic_data {
505         u32 base_offset;
506         u32 step;
507         u32 start_code;
508         unsigned gpio;
509         int gpio_en;
510         u32 i2c_slave_addr;
511         void (*pmic_bus_init)(void);
512         int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
513 };
514
515 /**
516  * struct volts_efuse_data - efuse definition for voltage
517  * @reg:        register address for efuse
518  * @reg_bits:   Number of bits in a register address, mandatory.
519  */
520 struct volts_efuse_data {
521         u32 reg;
522         u8 reg_bits;
523 };
524
525 struct volts {
526         u32 value;
527         u32 addr;
528         struct volts_efuse_data efuse;
529         struct pmic_data *pmic;
530 };
531
532 struct vcores_data {
533         struct volts mpu;
534         struct volts core;
535         struct volts mm;
536         struct volts gpu;
537         struct volts eve;
538         struct volts iva;
539 };
540
541 extern struct prcm_regs const **prcm;
542 extern struct prcm_regs const omap5_es1_prcm;
543 extern struct prcm_regs const omap5_es2_prcm;
544 extern struct prcm_regs const omap4_prcm;
545 extern struct prcm_regs const dra7xx_prcm;
546 extern struct dplls const **dplls_data;
547 extern struct vcores_data const **omap_vcores;
548 extern const u32 sys_clk_array[8];
549 extern struct omap_sys_ctrl_regs const **ctrl;
550 extern struct omap_sys_ctrl_regs const omap4_ctrl;
551 extern struct omap_sys_ctrl_regs const omap5_ctrl;
552 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
553
554 void hw_data_init(void);
555
556 const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
557 const struct dpll_params *get_core_dpll_params(struct dplls const *);
558 const struct dpll_params *get_per_dpll_params(struct dplls const *);
559 const struct dpll_params *get_iva_dpll_params(struct dplls const *);
560 const struct dpll_params *get_usb_dpll_params(struct dplls const *);
561 const struct dpll_params *get_abe_dpll_params(struct dplls const *);
562
563 void do_enable_clocks(u32 const *clk_domains,
564                       u32 const *clk_modules_hw_auto,
565                       u32 const *clk_modules_explicit_en,
566                       u8 wait_for_enable);
567
568 void setup_post_dividers(u32 const base,
569                         const struct dpll_params *params);
570 u32 omap_ddr_clk(void);
571 u32 get_sys_clk_index(void);
572 void enable_basic_clocks(void);
573 void enable_basic_uboot_clocks(void);
574 void enable_non_essential_clocks(void);
575 void scale_vcores(struct vcores_data const *);
576 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
577 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
578 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
579                u32 txdone, u32 txdone_mask, u32 opp);
580 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
581
582 /* HW Init Context */
583 #define OMAP_INIT_CONTEXT_SPL                   0
584 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR        1
585 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL       2
586 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH        3
587
588 /* ABB */
589 #define OMAP_ABB_NOMINAL_OPP            0
590 #define OMAP_ABB_FAST_OPP               1
591 #define OMAP_ABB_SLOW_OPP               3
592 #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK              (0x1 << 0)
593 #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK              (0x1 << 1)
594 #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK                (0x1 << 2)
595 #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK         (0x1 << 6)
596 #define OMAP_ABB_SETUP_SR2EN_MASK                       (0x1 << 0)
597 #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK              (0x1 << 2)
598 #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK              (0x1 << 1)
599 #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK             (0xff << 8)
600
601 static inline u32 omap_revision(void)
602 {
603         extern u32 *const omap_si_rev;
604         return *omap_si_rev;
605 }
606
607 #define OMAP54xx        0x54000000
608
609 static inline u8 is_omap54xx(void)
610 {
611         extern u32 *const omap_si_rev;
612         return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
613 }
614 #endif
615
616 /*
617  * silicon revisions.
618  * Moving this to common, so that most of code can be moved to common,
619  * directories.
620  */
621
622 /* omap4 */
623 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
624 #define OMAP4430_ES1_0  0x44300100
625 #define OMAP4430_ES2_0  0x44300200
626 #define OMAP4430_ES2_1  0x44300210
627 #define OMAP4430_ES2_2  0x44300220
628 #define OMAP4430_ES2_3  0x44300230
629 #define OMAP4460_ES1_0  0x44600100
630 #define OMAP4460_ES1_1  0x44600110
631
632 /* omap5 */
633 #define OMAP5430_SILICON_ID_INVALID     0
634 #define OMAP5430_ES1_0  0x54300100
635 #define OMAP5432_ES1_0  0x54320100
636 #define OMAP5430_ES2_0  0x54300200
637 #define OMAP5432_ES2_0  0x54320200
638
639 /* DRA7XX */
640 #define DRA752_ES1_0    0x07520100
641
642 /*
643  * SRAM scratch space entries
644  */
645 #define OMAP_SRAM_SCRATCH_OMAP_REV      SRAM_SCRATCH_SPACE_ADDR
646 #define OMAP_SRAM_SCRATCH_EMIF_SIZE     (SRAM_SCRATCH_SPACE_ADDR + 0x4)
647 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM    (SRAM_SCRATCH_SPACE_ADDR + 0xC)
648 #define OMAP_SRAM_SCRATCH_EMIF_T_DEN    (SRAM_SCRATCH_SPACE_ADDR + 0x10)
649 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
650 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
651 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
652 #define OMAP_SRAM_SCRATCH_SYS_CTRL      (SRAM_SCRATCH_SPACE_ADDR + 0x20)
653 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS   (SRAM_SCRATCH_SPACE_ADDR + 0x24)
654 #define OMAP5_SRAM_SCRATCH_SPACE_END    (SRAM_SCRATCH_SPACE_ADDR + 0x28)
655
656 #endif /* _OMAP_COMMON_H_ */