2 * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
4 * This program is used to generate definitions needed by
5 * assembly language modules.
7 * We use the technique used in the OSF Mach kernel code:
8 * generate asm statements containing #defines,
9 * compile this file to assembler, and then extract the
10 * #defines from the assembly-language output.
12 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/kbuild.h>
18 #if defined(CONFIG_MB86R0x)
19 #include <asm/arch/mb86r0x.h>
21 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
22 || defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
23 #include <asm/arch/imx-regs.h>
25 #if defined(CONFIG_MX6)
26 #include <asm/arch/crm_regs.h>
32 * TODO : Check if each entry in this file is really necessary.
33 * - struct mb86r0x_ddr2
34 * - struct mb86r0x_memc
35 * - struct esdramc_regs
41 * are used only for generating asm-offsets.h.
42 * It means their offset addresses are referenced only from assembly
43 * code. Is it better to define the macros directly in headers?
46 #if defined(CONFIG_MB86R0x)
48 DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
49 DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
50 DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
51 DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
52 DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
53 DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
54 DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
55 DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
56 DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
57 DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
58 DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
59 DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
60 DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
61 DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
62 DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
64 /* clock reset generator */
65 DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
66 DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
67 DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
68 DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
69 DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
70 DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
72 /* chip control module */
73 DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
75 /* external bus interface */
76 DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
77 DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
78 DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
79 DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
80 DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
81 DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
82 DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
83 DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
84 DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
87 #if defined(CONFIG_MX25)
88 /* Clock Control Module */
89 DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
90 DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
91 DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
92 DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
93 DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
94 DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
96 /* Enhanced SDRAM Controller */
97 DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
98 DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
99 DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
101 /* Multi-Layer AHB Crossbar Switch */
102 DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
103 DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
104 DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
105 DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
106 DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
107 DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
108 DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
109 DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
110 DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
111 DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
112 DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
113 DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
114 DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
115 DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
116 DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
118 /* AHB <-> IP-Bus Interface */
119 DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
120 DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
123 #if defined(CONFIG_MX27)
124 DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
125 DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
126 DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
127 DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
129 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
130 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
131 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
132 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
133 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
134 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
135 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
137 DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
138 DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
139 DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
140 DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
141 DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
143 DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
144 offsetof(struct system_control_regs, gpcr));
145 DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
146 offsetof(struct system_control_regs, fmcr));
149 #if defined(CONFIG_MX35)
150 /* Round up to make sure size gives nice stack alignment */
151 DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
152 DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
153 DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
154 DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
155 DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
156 DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
157 DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
158 DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
159 DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
160 DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
161 DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
162 DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
163 DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
164 DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
165 DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
167 /* Multi-Layer AHB Crossbar Switch */
168 DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
169 DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
170 DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
171 DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
172 DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
173 DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
174 DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
175 DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
176 DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
177 DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
178 DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
179 DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
180 DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
181 DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
182 DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
183 DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
185 /* AHB <-> IP-Bus Interface */
186 DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
187 DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
188 DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
189 DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
190 DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
191 DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
192 DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
193 DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
194 DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
195 DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
196 DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
199 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
200 /* Round up to make sure size gives nice stack alignment */
201 DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
202 DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
203 DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
204 DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
205 DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
206 DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
207 DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
208 DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
209 DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
210 DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
211 DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
212 DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
213 DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
214 DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
215 DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
216 DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
217 DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
218 DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
219 DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
220 DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
221 DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
222 DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
223 DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
224 DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
225 DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
226 DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
227 DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
228 DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
229 DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
230 DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
231 DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
232 DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
233 DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
234 DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
235 #if defined(CONFIG_MX53)
236 DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
240 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
241 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
242 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
243 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
244 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
245 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
246 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
247 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
249 #if defined(CONFIG_MX6)
250 DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
251 DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
252 DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
253 DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr));
254 DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr));
255 DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr));
256 DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr));
257 DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1));
258 DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2));
259 DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1));
260 DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr));
261 DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr));
262 DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr));
263 DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr));
264 DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2));
265 DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3));
266 DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4));
267 DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr));
268 DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr));
269 DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor));
270 DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr));
271 DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr));
272 DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr));
273 DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr));
274 DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr));
275 DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0));
276 DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1));
277 DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2));
278 DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3));
279 DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4));
280 DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5));
281 DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6));
282 DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7));
283 DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor));
285 DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet));