3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/system.h>
27 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
29 DECLARE_GLOBAL_DATA_PTR;
31 void __arm_init_before_mmu(void)
34 void arm_init_before_mmu(void)
35 __attribute__((weak, alias("__arm_init_before_mmu")));
37 void set_section_dcache(int section, enum dcache_option option)
39 u32 *page_table = (u32 *)gd->arch.tlb_addr;
42 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
44 page_table[section] = value;
47 void __mmu_page_table_flush(unsigned long start, unsigned long stop)
49 debug("%s: Warning: not implemented\n", __func__);
52 void mmu_page_table_flush(unsigned long start, unsigned long stop)
53 __attribute__((weak, alias("__mmu_page_table_flush")));
55 void mmu_set_region_dcache_behaviour(u32 start, int size,
56 enum dcache_option option)
58 u32 *page_table = (u32 *)gd->arch.tlb_addr;
61 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
62 start = start >> MMU_SECTION_SHIFT;
63 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
65 for (upto = start; upto < end; upto++)
66 set_section_dcache(upto, option);
67 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
70 static inline void dram_bank_mmu_setup(int bank)
75 debug("%s: bank: %d\n", __func__, bank);
76 for (i = bd->bi_dram[bank].start >> 20;
77 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
79 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
80 set_section_dcache(i, DCACHE_WRITETHROUGH);
82 set_section_dcache(i, DCACHE_WRITEBACK);
87 /* to activate the MMU we need to set up virtual memory: use 1M areas */
88 static inline void mmu_setup(void)
90 u32 *page_table = (u32 *)gd->arch.tlb_addr;
94 arm_init_before_mmu();
95 /* Set up an identity-mapping for all 4GB, rw for everyone */
96 for (i = 0; i < 4096; i++)
97 set_section_dcache(i, DCACHE_OFF);
99 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
100 dram_bank_mmu_setup(i);
104 /* Copy the page table address to cp15 */
105 "mcr p15, 0, %0, c2, c0, 0\n"
106 /* Set the access control to all-supervisor */
107 "mcr p15, 0, %1, c3, c0, 0\n"
109 : "r"(page_table), "r"(~0)
111 /* and enable the mmu */
112 reg = get_cr(); /* get control reg. */
116 static int mmu_enabled(void)
118 return get_cr() & CR_M;
121 /* cache_bit must be either CR_I or CR_C */
122 static void cache_enable(uint32_t cache_bit)
126 /* The data cache is not active unless the mmu is enabled too */
127 if ((cache_bit == CR_C) && !mmu_enabled())
129 reg = get_cr(); /* get control reg. */
130 set_cr(reg | cache_bit);
133 /* cache_bit must be either CR_I or CR_C */
134 static void cache_disable(uint32_t cache_bit)
140 if (cache_bit == CR_C) {
141 /* if cache isn;t enabled no need to disable */
142 if ((reg & CR_C) != CR_C)
144 /* if disabling data cache, disable mmu too */
148 if (cache_bit == (CR_C | CR_M))
150 set_cr(reg & ~cache_bit);
154 #ifdef CONFIG_SYS_ICACHE_OFF
155 void icache_enable (void)
160 void icache_disable (void)
165 int icache_status (void)
167 return 0; /* always off */
170 void icache_enable(void)
175 void icache_disable(void)
180 int icache_status(void)
182 return (get_cr() & CR_I) != 0;
186 #ifdef CONFIG_SYS_DCACHE_OFF
187 void dcache_enable (void)
192 void dcache_disable (void)
197 int dcache_status (void)
199 return 0; /* always off */
202 void dcache_enable(void)
207 void dcache_disable(void)
212 int dcache_status(void)
214 return (get_cr() & CR_C) != 0;