arch/blackfin/cpu/initcode.c

   1 /*
   2  * initcode.c - Initialize the processor.  This is usually entails things
   3  * like external memory, voltage regulators, etc...  Note that this file
   4  * cannot make any function calls as it may be executed all by itself by
   5  * the Blackfin's bootrom in LDR format.
   6  *
   7  * Copyright (c) 2004-2011 Analog Devices Inc.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #define BFIN_IN_INITCODE
  13
  14 #include <config.h>
  15 #include <asm/blackfin.h>
  16 #include <asm/mach-common/bits/bootrom.h>
  17 #include <asm/mach-common/bits/core.h>
  18
  19 #define BUG() while (1) { asm volatile("emuexcpt;"); }
  20
  21 #include "serial.h"
  22
  23 #ifndef __ADSPBF60x__
  24 #include <asm/mach-common/bits/ebiu.h>
  25 #include <asm/mach-common/bits/pll.h>
  26 #else /* __ADSPBF60x__ */
  27 #include <asm/mach-common/bits/cgu.h>
  28
  29 #define CONFIG_BFIN_GET_DCLK_M \
  30         ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
  31
  32 #ifndef CONFIG_DMC_DDRCFG
  33 #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
  34         (CONFIG_BFIN_GET_DCLK_M != 133) && \
  35         (CONFIG_BFIN_GET_DCLK_M != 150) && \
  36         (CONFIG_BFIN_GET_DCLK_M != 166) && \
  37         (CONFIG_BFIN_GET_DCLK_M != 200) && \
  38         (CONFIG_BFIN_GET_DCLK_M != 225) && \
  39         (CONFIG_BFIN_GET_DCLK_M != 250))
  40 #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  41 #endif
  42 #endif
  43
  44 /* DMC control bits */
  45 #define SRREQ                   0x8
  46
  47 /* DMC status bits */
  48 #define IDLE                    0x1
  49 #define MEMINITDONE             0x4
  50 #define SRACK                   0x8
  51 #define PDACK                   0x10
  52 #define DPDACK                  0x20
  53 #define DLLCALDONE              0x2000
  54 #define PENDREF                 0xF0000
  55 #define PHYRDPHASE              0xF00000
  56 #define PHYRDPHASE_OFFSET       20
  57
  58 /* DMC DLL control bits */
  59 #define DLLCALRDCNT             0xFF
  60 #define DATACYC_OFFSET          8
  61
  62 struct ddr_config {
  63         u32 ddr_clk;
  64         u32 dmc_ddrctl;
  65         u32 dmc_ddrcfg;
  66         u32 dmc_ddrtr0;
  67         u32 dmc_ddrtr1;
  68         u32 dmc_ddrtr2;
  69         u32 dmc_ddrmr;
  70         u32 dmc_ddrmr1;
  71 };
  72
  73 static struct ddr_config ddr_config_table[] = {
  74         [0] = {
  75                 .ddr_clk    = 125,      /* 125MHz */
  76                 .dmc_ddrctl = 0x00000904,
  77                 .dmc_ddrcfg = 0x00000422,
  78                 .dmc_ddrtr0 = 0x20705212,
  79                 .dmc_ddrtr1 = 0x201003CF,
  80                 .dmc_ddrtr2 = 0x00320107,
  81                 .dmc_ddrmr  = 0x00000422,
  82                 .dmc_ddrmr1 = 0x4,
  83         },
  84         [1] = {
  85                 .ddr_clk    = 133,      /* 133MHz */
  86                 .dmc_ddrctl = 0x00000904,
  87                 .dmc_ddrcfg = 0x00000422,
  88                 .dmc_ddrtr0 = 0x20806313,
  89                 .dmc_ddrtr1 = 0x2013040D,
  90                 .dmc_ddrtr2 = 0x00320108,
  91                 .dmc_ddrmr  = 0x00000632,
  92                 .dmc_ddrmr1 = 0x4,
  93         },
  94         [2] = {
  95                 .ddr_clk    = 150,      /* 150MHz */
  96                 .dmc_ddrctl = 0x00000904,
  97                 .dmc_ddrcfg = 0x00000422,
  98                 .dmc_ddrtr0 = 0x20A07323,
  99                 .dmc_ddrtr1 = 0x20160492,
 100                 .dmc_ddrtr2 = 0x00320209,
 101                 .dmc_ddrmr  = 0x00000632,
 102                 .dmc_ddrmr1 = 0x4,
 103         },
 104         [3] = {
 105                 .ddr_clk    = 166,      /* 166MHz */
 106                 .dmc_ddrctl = 0x00000904,
 107                 .dmc_ddrcfg = 0x00000422,
 108                 .dmc_ddrtr0 = 0x20A07323,
 109                 .dmc_ddrtr1 = 0x2016050E,
 110                 .dmc_ddrtr2 = 0x00320209,
 111                 .dmc_ddrmr  = 0x00000632,
 112                 .dmc_ddrmr1 = 0x4,
 113         },
 114         [4] = {
 115                 .ddr_clk    = 200,      /* 200MHz */
 116                 .dmc_ddrctl = 0x00000904,
 117                 .dmc_ddrcfg = 0x00000422,
 118                 .dmc_ddrtr0 = 0x20a07323,
 119                 .dmc_ddrtr1 = 0x2016050f,
 120                 .dmc_ddrtr2 = 0x00320509,
 121                 .dmc_ddrmr  = 0x00000632,
 122                 .dmc_ddrmr1 = 0x4,
 123         },
 124         [5] = {
 125                 .ddr_clk    = 225,      /* 225MHz */
 126                 .dmc_ddrctl = 0x00000904,
 127                 .dmc_ddrcfg = 0x00000422,
 128                 .dmc_ddrtr0 = 0x20E0A424,
 129                 .dmc_ddrtr1 = 0x302006DB,
 130                 .dmc_ddrtr2 = 0x0032020D,
 131                 .dmc_ddrmr  = 0x00000842,
 132                 .dmc_ddrmr1 = 0x4,
 133         },
 134         [6] = {
 135                 .ddr_clk    = 250,      /* 250MHz */
 136                 .dmc_ddrctl = 0x00000904,
 137                 .dmc_ddrcfg = 0x00000422,
 138                 .dmc_ddrtr0 = 0x20E0A424,
 139                 .dmc_ddrtr1 = 0x3020079E,
 140                 .dmc_ddrtr2 = 0x0032050D,
 141                 .dmc_ddrmr  = 0x00000842,
 142                 .dmc_ddrmr1 = 0x4,
 143         },
 144 };
 145 #endif /* __ADSPBF60x__ */
 146
 147 __attribute__((always_inline))
 148 static inline void serial_init(void)
 149 {
 150         uint32_t uart_base = UART_BASE;
 151
 152 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 153 # ifdef BFIN_BOOT_UART_USE_RTS
 154 #  define BFIN_UART_USE_RTS 1
 155 # else
 156 #  define BFIN_UART_USE_RTS 0
 157 # endif
 158         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 159                 size_t i;
 160
 161                 /* force RTS rather than relying on auto RTS */
 162 #if BFIN_UART_HW_VER < 4
 163                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
 164 #else
 165                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
 166                                 FCPOL);
 167 #endif
 168
 169                 /* Wait for the line to clear up.  We cannot rely on UART
 170                  * registers as none of them reflect the status of the RSR.
 171                  * Instead, we'll sleep for ~10 bit times at 9600 baud.
 172                  * We can precalc things here by assuming boot values for
 173                  * PLL rather than loading registers and calculating.
 174                  *      baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
 175                  *      EDB0    = 0
 176                  *      Divisor = (SCLK / baud) / 16
 177                  *      SCLK    = baud * 16 * Divisor
 178                  *      SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
 179                  *      CCLK    = (16 * Divisor * 5) * (9600 / 10)
 180                  * In reality, this will probably be just about 1 second delay,
 181                  * so assuming 9600 baud is OK (both as a very low and too high
 182                  * speed as this will buffer things enough).
 183                  */
 184 #define _NUMBITS (10)                                   /* how many bits to delay */
 185 #define _LOWBAUD (9600)                                 /* low baud rate */
 186 #define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
 187 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
 188 #define _NUMINS  (3)                                    /* how many instructions in loop */
 189 #define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
 190                 i = _CCLK;
 191                 while (i--)
 192                         asm volatile("" : : : "memory");
 193         }
 194 #endif
 195
 196         if (BFIN_DEBUG_EARLY_SERIAL) {
 197                 int enabled = serial_early_enabled(uart_base);
 198
 199                 serial_early_init(uart_base);
 200
 201                 /* If the UART is off, that means we need to program
 202                  * the baud rate ourselves initially.
 203                  */
 204                 if (!enabled)
 205                         serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 206         }
 207 }
 208
 209 __attribute__((always_inline))
 210 static inline void serial_deinit(void)
 211 {
 212 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 213         uint32_t uart_base = UART_BASE;
 214
 215         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 216                 /* clear forced RTS rather than relying on auto RTS */
 217 #if BFIN_UART_HW_VER < 4
 218                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
 219 #else
 220                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
 221                                 ~FCPOL);
 222 #endif
 223         }
 224 #endif
 225 }
 226
 227 __attribute__((always_inline))
 228 static inline void serial_putc(char c)
 229 {
 230         uint32_t uart_base = UART_BASE;
 231
 232         if (!BFIN_DEBUG_EARLY_SERIAL)
 233                 return;
 234
 235         if (c == '\n')
 236                 serial_putc('\r');
 237
 238         bfin_write(&pUART->thr, c);
 239
 240         while (!(_lsr_read(pUART) & TEMT))
 241                 continue;
 242 }
 243
 244 #include "initcode.h"
 245
 246 __attribute__((always_inline)) static inline void
 247 program_nmi_handler(void)
 248 {
 249         u32 tmp1, tmp2;
 250
 251         /* Older bootroms don't create a dummy NMI handler,
 252          * so make one ourselves ASAP in case it fires.
 253          */
 254         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
 255                 return;
 256
 257         asm volatile (
 258                 "%0 = RETS;" /* Save current RETS */
 259                 "CALL 1f;"   /* Figure out current PC */
 260                 "RTN;"       /* The simple NMI handler */
 261                 "1:"
 262                 "%1 = RETS;" /* Load addr of NMI handler */
 263                 "RETS = %0;" /* Restore RETS */
 264                 "[%2] = %1;" /* Write NMI handler */
 265                 : "=d"(tmp1), "=d"(tmp2)
 266                 : "ab"(EVT2)
 267         );
 268 }
 269
 270 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
 271  * us a freq of 16MHz for SPI which should generally be
 272  * slow enough for the slow reads the bootrom uses.
 273  */
 274 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
 275     ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
 276      (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
 277 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
 278 #else
 279 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
 280 #endif
 281 #ifndef CONFIG_SPI_BAUD_INITBLOCK
 282 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
 283 #endif
 284 #ifdef SPI0_BAUD
 285 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 286 #endif
 287
 288 #ifdef __ADSPBF60x__
 289
 290 #ifndef CONFIG_CGU_CTL_VAL
 291 # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
 292 #endif
 293
 294 #ifndef CONFIG_CGU_DIV_VAL
 295 # define CONFIG_CGU_DIV_VAL \
 296         ((CONFIG_CCLK_DIV   << CSEL_P)   | \
 297          (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
 298          (CONFIG_SCLK_DIV << SYSSEL_P) | \
 299          (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
 300          (CONFIG_DCLK_DIV   << DSEL_P)   | \
 301          (CONFIG_OCLK_DIV   << OSEL_P))
 302 #endif
 303
 304 #else /* __ADSPBF60x__ */
 305
 306 /* PLL_DIV defines */
 307 #ifndef CONFIG_PLL_DIV_VAL
 308 # if (CONFIG_CCLK_DIV == 1)
 309 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
 310 # elif (CONFIG_CCLK_DIV == 2)
 311 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
 312 # elif (CONFIG_CCLK_DIV == 4)
 313 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
 314 # elif (CONFIG_CCLK_DIV == 8)
 315 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
 316 # else
 317 #  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
 318 # endif
 319 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
 320 #endif
 321
 322 #ifndef CONFIG_PLL_LOCKCNT_VAL
 323 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
 324 #endif
 325
 326 #ifndef CONFIG_PLL_CTL_VAL
 327 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
 328 #endif
 329
 330 /* Make sure our voltage value is sane so we don't blow up! */
 331 #ifndef CONFIG_VR_CTL_VAL
 332 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
 333 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
 334 #  define CCLK_VLEV_120 400000000
 335 #  define CCLK_VLEV_125 533000000
 336 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
 337 #  define CCLK_VLEV_120 401000000
 338 #  define CCLK_VLEV_125 401000000
 339 # elif defined(__ADSPBF561__)
 340 #  define CCLK_VLEV_120 300000000
 341 #  define CCLK_VLEV_125 501000000
 342 # endif
 343 # if BFIN_CCLK < CCLK_VLEV_120
 344 #  define CONFIG_VR_CTL_VLEV VLEV_120
 345 # elif BFIN_CCLK < CCLK_VLEV_125
 346 #  define CONFIG_VR_CTL_VLEV VLEV_125
 347 # else
 348 #  define CONFIG_VR_CTL_VLEV VLEV_130
 349 # endif
 350 # if defined(__ADSPBF52x__)     /* TBD; use default */
 351 #  undef CONFIG_VR_CTL_VLEV
 352 #  define CONFIG_VR_CTL_VLEV VLEV_110
 353 # elif defined(__ADSPBF54x__)   /* TBD; use default */
 354 #  undef CONFIG_VR_CTL_VLEV
 355 #  define CONFIG_VR_CTL_VLEV VLEV_120
 356 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
 357 #  undef CONFIG_VR_CTL_VLEV
 358 #  define CONFIG_VR_CTL_VLEV VLEV_125
 359 # endif
 360
 361 # ifdef CONFIG_BFIN_MAC
 362 #  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
 363 # else
 364 #  define CONFIG_VR_CTL_CLKBUF 0
 365 # endif
 366
 367 # if defined(__ADSPBF52x__)
 368 #  define CONFIG_VR_CTL_FREQ FREQ_1000
 369 # else
 370 #  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
 371 # endif
 372
 373 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 374 #endif
 375
 376 /* some parts do not have an on-chip voltage regulator */
 377 #if defined(__ADSPBF51x__)
 378 # define CONFIG_HAS_VR 0
 379 # undef CONFIG_VR_CTL_VAL
 380 # define CONFIG_VR_CTL_VAL 0
 381 #else
 382 # define CONFIG_HAS_VR 1
 383 #endif
 384
 385 #if CONFIG_MEM_SIZE
 386 #ifndef EBIU_RSTCTL
 387 /* Blackfin with SDRAM */
 388 #ifndef CONFIG_EBIU_SDBCTL_VAL
 389 # if CONFIG_MEM_SIZE == 16
 390 #  define CONFIG_EBSZ_VAL EBSZ_16
 391 # elif CONFIG_MEM_SIZE == 32
 392 #  define CONFIG_EBSZ_VAL EBSZ_32
 393 # elif CONFIG_MEM_SIZE == 64
 394 #  define CONFIG_EBSZ_VAL EBSZ_64
 395 # elif CONFIG_MEM_SIZE == 128
 396 #  define CONFIG_EBSZ_VAL EBSZ_128
 397 # elif CONFIG_MEM_SIZE == 256
 398 #  define CONFIG_EBSZ_VAL EBSZ_256
 399 # elif CONFIG_MEM_SIZE == 512
 400 #  define CONFIG_EBSZ_VAL EBSZ_512
 401 # else
 402 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
 403 # endif
 404 # if CONFIG_MEM_ADD_WDTH == 8
 405 #  define CONFIG_EBCAW_VAL EBCAW_8
 406 # elif CONFIG_MEM_ADD_WDTH == 9
 407 #  define CONFIG_EBCAW_VAL EBCAW_9
 408 # elif CONFIG_MEM_ADD_WDTH == 10
 409 #  define CONFIG_EBCAW_VAL EBCAW_10
 410 # elif CONFIG_MEM_ADD_WDTH == 11
 411 #  define CONFIG_EBCAW_VAL EBCAW_11
 412 # else
 413 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
 414 # endif
 415 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
 416 #endif
 417 #endif
 418 #endif
 419
 420 /* Conflicting Column Address Widths Causes SDRAM Errors:
 421  * EB2CAW and EB3CAW must be the same
 422  */
 423 #if ANOMALY_05000362
 424 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
 425 #  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
 426 # endif
 427 #endif
 428
 429 #endif /*  __ADSPBF60x__ */
 430
 431 __attribute__((always_inline)) static inline void
 432 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 433 {
 434         serial_putc('a');
 435
 436         /* Save the clock pieces that are used in baud rate calculation */
 437         if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 438                 serial_putc('b');
 439 #ifdef __ADSPBF60x__
 440                 *sdivB = bfin_read_CGU_DIV();
 441                 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
 442                 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 443 #else
 444                 *sdivB = bfin_read_PLL_DIV() & 0xf;
 445                 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 446 #endif
 447                 *divB = serial_early_get_div();
 448                 serial_putc('c');
 449         }
 450
 451         serial_putc('d');
 452
 453 #ifdef CONFIG_HW_WATCHDOG
 454 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 455 #  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
 456 # endif
 457         /* Program the watchdog with an initial timeout of ~20 seconds.
 458          * Hopefully that should be long enough to load the u-boot LDR
 459          * (from wherever) and then the common u-boot code can take over.
 460          * In bypass mode, the start.S would have already set a much lower
 461          * timeout, so don't clobber that.
 462          */
 463         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 464                 serial_putc('e');
 465 #ifdef __ADSPBF60x__
 466                 bfin_write_SEC_GCTL(0x2);
 467                 SSYNC();
 468                 bfin_write_SEC_FCTL(0xc1);
 469                 bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
 470
 471                 bfin_write_SEC_CCTL(0x2);
 472                 SSYNC();
 473                 bfin_write_SEC_GCTL(0x1);
 474                 bfin_write_SEC_CCTL(0x1);
 475 #endif
 476                 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
 477 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
 478                 bfin_write_WDOG_CTL(0);
 479 #endif
 480                 serial_putc('f');
 481         }
 482 #endif
 483
 484         serial_putc('g');
 485
 486         /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
 487          * fast read, so we need to slow down the SPI clock a lot more during
 488          * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 489          * increase the speed appropriately.
 490          */
 491 #ifdef SPI_BAUD
 492         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
 493                 serial_putc('h');
 494                 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
 495                         bs->dFlags |= BFLAG_FASTREAD;
 496                 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
 497                 serial_putc('i');
 498         }
 499 #endif
 500
 501         serial_putc('j');
 502 }
 503
 504 __attribute__((always_inline)) static inline bool
 505 maybe_self_refresh(ADI_BOOT_DATA *bs)
 506 {
 507         serial_putc('a');
 508
 509         if (!CONFIG_MEM_SIZE)
 510                 return false;
 511
 512 #ifdef __ADSPBF60x__
 513         /* resume from hibernate, return false let ddr initialize */
 514         if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
 515                 serial_putc('b');
 516                 return false;
 517         }
 518
 519 #else /* __ADSPBF60x__ */
 520
 521         /* If external memory is enabled, put it into self refresh first. */
 522 #if defined(EBIU_RSTCTL)
 523         if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
 524                 serial_putc('b');
 525                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
 526                 return true;
 527         }
 528 #elif defined(EBIU_SDGCTL)
 529         if (bfin_read_EBIU_SDBCTL() & EBE) {
 530                 serial_putc('b');
 531                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
 532                 return true;
 533         }
 534 #endif
 535
 536 #endif /* __ADSPBF60x__ */
 537         serial_putc('c');
 538
 539         return false;
 540 }
 541
 542 __attribute__((always_inline)) static inline u16
 543 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 544 {
 545         u16 vr_ctl;
 546
 547         serial_putc('a');
 548
 549 #ifdef __ADSPBF60x__
 550         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 551                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
 552                 SSYNC();
 553                 while (!(bfin_read_DMC0_STAT() & SRACK))
 554                         continue;
 555         }
 556
 557         /* Don't set the same value of MSEL and DF to CGU_CTL */
 558         if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
 559                         != CONFIG_CGU_CTL_VAL) {
 560                 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
 561                 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
 562                 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
 563                                 !(bfin_read_CGU_STAT() & PLLLK))
 564                         continue;
 565         }
 566
 567         bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
 568         while (bfin_read_CGU_STAT() & CLKSALGN)
 569                 continue;
 570
 571         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 572                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
 573                 SSYNC();
 574                 while (bfin_read_DMC0_STAT() & SRACK)
 575                         continue;
 576         }
 577
 578 #else /* __ADSPBF60x__ */
 579
 580         vr_ctl = bfin_read_VR_CTL();
 581
 582         serial_putc('b');
 583
 584         /* If we're entering self refresh, make sure it has happened. */
 585         if (put_into_srfs)
 586 #if defined(EBIU_RSTCTL)
 587                 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
 588                         continue;
 589 #elif defined(EBIU_SDGCTL)
 590                 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
 591                         continue;
 592 #else
 593                 ;
 594 #endif
 595
 596         serial_putc('c');
 597
 598         /* With newer bootroms, we use the helper function to set up
 599          * the memory controller.  Older bootroms lacks such helpers
 600          * so we do it ourselves.
 601          */
 602         if (!ANOMALY_05000386) {
 603                 serial_putc('d');
 604
 605                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 606                 ADI_SYSCTRL_VALUES memory_settings;
 607                 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
 608                 if (!ANOMALY_05000440)
 609                         actions |= SYSCTRL_PLLDIV;
 610                 if (CONFIG_HAS_VR) {
 611                         actions |= SYSCTRL_VRCTL;
 612                         if (CONFIG_VR_CTL_VAL & FREQ_MASK)
 613                                 actions |= SYSCTRL_INTVOLTAGE;
 614                         else
 615                                 actions |= SYSCTRL_EXTVOLTAGE;
 616                         memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
 617                 } else
 618                         actions |= SYSCTRL_EXTVOLTAGE;
 619                 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
 620                 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
 621                 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
 622 #if ANOMALY_05000432
 623                 bfin_write_SIC_IWR1(0);
 624 #endif
 625                 serial_putc('e');
 626                 bfrom_SysControl(actions, &memory_settings, NULL);
 627                 serial_putc('f');
 628                 if (ANOMALY_05000440)
 629                         bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 630 #if ANOMALY_05000432
 631                 bfin_write_SIC_IWR1(-1);
 632 #endif
 633 #if ANOMALY_05000171
 634                 bfin_write_SICA_IWR0(-1);
 635                 bfin_write_SICA_IWR1(-1);
 636 #endif
 637                 serial_putc('g');
 638         } else {
 639                 serial_putc('h');
 640
 641                 /* Disable all peripheral wakeups except for the PLL event. */
 642 #ifdef SIC_IWR0
 643                 bfin_write_SIC_IWR0(1);
 644                 bfin_write_SIC_IWR1(0);
 645 # ifdef SIC_IWR2
 646                 bfin_write_SIC_IWR2(0);
 647 # endif
 648 #elif defined(SICA_IWR0)
 649                 bfin_write_SICA_IWR0(1);
 650                 bfin_write_SICA_IWR1(0);
 651 #elif defined(SIC_IWR)
 652                 bfin_write_SIC_IWR(1);
 653 #endif
 654
 655                 serial_putc('i');
 656
 657                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 658                 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 659
 660                 serial_putc('j');
 661
 662                 /* Only reprogram when needed to avoid triggering unnecessary
 663                  * PLL relock sequences.
 664                  */
 665                 if (vr_ctl != CONFIG_VR_CTL_VAL) {
 666                         serial_putc('?');
 667                         bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
 668                         asm("idle;");
 669                         serial_putc('!');
 670                 }
 671
 672                 serial_putc('k');
 673
 674                 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 675
 676                 serial_putc('l');
 677
 678                 /* Only reprogram when needed to avoid triggering unnecessary
 679                  * PLL relock sequences.
 680                  */
 681                 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 682                         serial_putc('?');
 683                         bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 684                         asm("idle;");
 685                         serial_putc('!');
 686                 }
 687
 688                 serial_putc('m');
 689
 690                 /* Restore all peripheral wakeups. */
 691 #ifdef SIC_IWR0
 692                 bfin_write_SIC_IWR0(-1);
 693                 bfin_write_SIC_IWR1(-1);
 694 # ifdef SIC_IWR2
 695                 bfin_write_SIC_IWR2(-1);
 696 # endif
 697 #elif defined(SICA_IWR0)
 698                 bfin_write_SICA_IWR0(-1);
 699                 bfin_write_SICA_IWR1(-1);
 700 #elif defined(SIC_IWR)
 701                 bfin_write_SIC_IWR(-1);
 702 #endif
 703
 704                 serial_putc('n');
 705         }
 706
 707 #endif /* __ADSPBF60x__ */
 708
 709         serial_putc('o');
 710
 711         return vr_ctl;
 712 }
 713
 714 __attribute__((always_inline)) static inline void
 715 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 716 {
 717         serial_putc('a');
 718
 719         /* Since we've changed the SCLK above, we may need to update
 720          * the UART divisors (UART baud rates are based on SCLK).
 721          * Do the division by hand as there are no native instructions
 722          * for dividing which means we'd generate a libgcc reference.
 723          */
 724         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 725                 unsigned int sdivR, vcoR;
 726                 int dividend = sdivB * divB * vcoR;
 727                 int divisor = vcoB * sdivR;
 728                 unsigned int quotient;
 729
 730                 serial_putc('b');
 731
 732 #ifdef __ADSPBF60x__
 733                 sdivR = bfin_read_CGU_DIV();
 734                 sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
 735                 vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 736 #else
 737                 sdivR = bfin_read_PLL_DIV() & 0xf;
 738                 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 739 #endif
 740
 741                 for (quotient = 0; dividend > 0; ++quotient)
 742                         dividend -= divisor;
 743                 serial_early_put_div(quotient - ANOMALY_05000230);
 744                 serial_putc('c');
 745         }
 746
 747         serial_putc('d');
 748 }
 749
 750 __attribute__((always_inline)) static inline void
 751 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 752 {
 753         serial_putc('a');
 754
 755         if (!CONFIG_MEM_SIZE)
 756                 return;
 757
 758         serial_putc('b');
 759
 760 #ifdef __ADSPBF60x__
 761         int dlldatacycle;
 762         int dll_ctl;
 763         int i = 0;
 764
 765         if (CONFIG_BFIN_GET_DCLK_M ==  125)
 766                 i = 0;
 767         else if (CONFIG_BFIN_GET_DCLK_M ==  133)
 768                 i = 1;
 769         else if (CONFIG_BFIN_GET_DCLK_M ==  150)
 770                 i = 2;
 771         else if (CONFIG_BFIN_GET_DCLK_M ==  166)
 772                 i = 3;
 773         else if (CONFIG_BFIN_GET_DCLK_M ==  200)
 774                 i = 4;
 775         else if (CONFIG_BFIN_GET_DCLK_M ==  225)
 776                 i = 5;
 777         else if (CONFIG_BFIN_GET_DCLK_M ==  250)
 778                 i = 6;
 779
 780 #if 0
 781         for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
 782                 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
 783                         break;
 784 #endif
 785
 786 #ifndef CONFIG_DMC_DDRCFG
 787         bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
 788 #else
 789         bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
 790 #endif
 791 #ifndef CONFIG_DMC_DDRTR0
 792         bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
 793 #else
 794         bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
 795 #endif
 796 #ifndef CONFIG_DMC_DDRTR1
 797         bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
 798 #else
 799         bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
 800 #endif
 801 #ifndef CONFIG_DMC_DDRTR2
 802         bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
 803 #else
 804         bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
 805 #endif
 806 #ifndef CONFIG_DMC_DDRMR
 807         bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
 808 #else
 809         bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
 810 #endif
 811 #ifndef CONFIG_DMC_DDREMR1
 812         bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
 813 #else
 814         bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
 815 #endif
 816 #ifndef CONFIG_DMC_DDRCTL
 817         bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
 818 #else
 819         bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
 820 #endif
 821
 822         SSYNC();
 823         while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
 824                 continue;
 825
 826         dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
 827                         PHYRDPHASE_OFFSET;
 828         dll_ctl = bfin_read_DMC0_DLLCTL();
 829         dll_ctl &= 0x0ff;
 830         bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
 831
 832         SSYNC();
 833         while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
 834                 continue;
 835         serial_putc('!');
 836
 837 #else /* __ADSPBF60x__ */
 838
 839         /* Program the external memory controller before we come out of
 840          * self-refresh.  This only works with our SDRAM controller.
 841          */
 842 #ifdef EBIU_SDGCTL
 843 # ifdef CONFIG_EBIU_SDRRC_VAL
 844         bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
 845 # endif
 846 # ifdef CONFIG_EBIU_SDBCTL_VAL
 847         bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
 848 # endif
 849 # ifdef CONFIG_EBIU_SDGCTL_VAL
 850         bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
 851 # endif
 852 #endif
 853
 854         serial_putc('c');
 855
 856         /* Now that we've reprogrammed, take things out of self refresh. */
 857         if (put_into_srfs)
 858 #if defined(EBIU_RSTCTL)
 859                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
 860 #elif defined(EBIU_SDGCTL)
 861                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
 862 #endif
 863
 864         serial_putc('d');
 865
 866         /* Our DDR controller sucks and cannot be programmed while in
 867          * self-refresh.  So we have to pull it out before programming.
 868          */
 869 #ifdef EBIU_RSTCTL
 870 # ifdef CONFIG_EBIU_RSTCTL_VAL
 871         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
 872 # endif
 873 # ifdef CONFIG_EBIU_DDRCTL0_VAL
 874         bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
 875 # endif
 876 # ifdef CONFIG_EBIU_DDRCTL1_VAL
 877         bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
 878 # endif
 879 # ifdef CONFIG_EBIU_DDRCTL2_VAL
 880         bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
 881 # endif
 882 # ifdef CONFIG_EBIU_DDRCTL3_VAL
 883         /* default is disable, so don't need to force this */
 884         bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
 885 # endif
 886 # ifdef CONFIG_EBIU_DDRQUE_VAL
 887         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
 888 # endif
 889 #endif
 890
 891 #endif /* __ADSPBF60x__ */
 892         serial_putc('e');
 893 }
 894
 895 __attribute__((always_inline)) static inline void
 896 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 897 {
 898         serial_putc('a');
 899
 900         if (!CONFIG_MEM_SIZE)
 901                 return;
 902
 903         serial_putc('b');
 904 #ifdef __ADSPBF60x__
 905         if (bfin_read32(DPM0_RESTORE0) != 0) {
 906                 uint32_t reg = bfin_read_DMC0_CTL();
 907                 reg &= ~0x8;
 908                 bfin_write_DMC0_CTL(reg);
 909
 910                 while ((bfin_read_DMC0_STAT() & 0x8))
 911                         continue;
 912                 while (!(bfin_read_DMC0_STAT() & 0x1))
 913                         continue;
 914
 915                 serial_putc('z');
 916                 uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
 917                 SSYNC(); /* make sure memory controller is done */
 918                 if (hibernate_magic[0] == 0xDEADBEEF) {
 919                         serial_putc('c');
 920                         SSYNC();
 921                         bfin_write_EVT15(hibernate_magic[1]);
 922                         bfin_write_IMASK(EVT_IVG15);
 923                         __asm__ __volatile__ (
 924                                 /* load reti early to avoid anomaly 281 */
 925                                 "reti = %2;"
 926                                 /* clear hibernate magic */
 927                                 "[%0] = %1;"
 928                                 /* load stack pointer */
 929                                 "SP = [%0 + 8];"
 930                                 /* lower ourselves from reset ivg to ivg15 */
 931                                 "raise 15;"
 932                                 "nop;nop;nop;"
 933                                 "rti;"
 934                                 :
 935                                 : "p"(hibernate_magic),
 936                                 "d"(0x2000 /* jump.s 0 */),
 937                                 "d"(0xffa00000)
 938                         );
 939                 }
 940
 941
 942         }
 943 #else
 944         /* Are we coming out of hibernate (suspend to memory) ?
 945          * The memory layout is:
 946          * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
 947          * 0x4: return address
 948          * 0x8: stack pointer
 949          *
 950          * SCKELOW is unreliable on older parts (anomaly 307)
 951          */
 952         if (ANOMALY_05000307 || vr_ctl & 0x8000) {
 953                 uint32_t *hibernate_magic = 0;
 954
 955                 SSYNC();
 956                 if (hibernate_magic[0] == 0xDEADBEEF) {
 957                         serial_putc('c');
 958                         bfin_write_EVT15(hibernate_magic[1]);
 959                         bfin_write_IMASK(EVT_IVG15);
 960                         __asm__ __volatile__ (
 961                                 /* load reti early to avoid anomaly 281 */
 962                                 "reti = %0;"
 963                                 /* clear hibernate magic */
 964                                 "[%0] = %1;"
 965                                 /* load stack pointer */
 966                                 "SP = [%0 + 8];"
 967                                 /* lower ourselves from reset ivg to ivg15 */
 968                                 "raise 15;"
 969                                 "rti;"
 970                                 :
 971                                 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
 972                         );
 973                 }
 974                 serial_putc('d');
 975         }
 976 #endif
 977
 978         serial_putc('e');
 979 }
 980
 981 BOOTROM_CALLED_FUNC_ATTR
 982 void initcode(ADI_BOOT_DATA *bs)
 983 {
 984         ADI_BOOT_DATA bootstruct_scratch;
 985
 986         /* Setup NMI handler before anything else */
 987         program_nmi_handler();
 988
 989         serial_init();
 990
 991         serial_putc('A');
 992
 993         /* If the bootstruct is NULL, then it's because we're loading
 994          * dynamically and not via LDR (bootrom).  So set the struct to
 995          * some scratch space.
 996          */
 997         if (!bs)
 998                 bs = &bootstruct_scratch;
 999
1000         serial_putc('B');
1001         bool put_into_srfs = maybe_self_refresh(bs);
1002
1003         serial_putc('C');
1004         uint sdivB, divB, vcoB;
1005         program_early_devices(bs, &sdivB, &divB, &vcoB);
1006
1007         serial_putc('D');
1008         u16 vr_ctl = program_clocks(bs, put_into_srfs);
1009
1010         serial_putc('E');
1011         update_serial_clocks(bs, sdivB, divB, vcoB);
1012
1013         serial_putc('F');
1014         program_memory_controller(bs, put_into_srfs);
1015
1016         serial_putc('G');
1017         check_hibernation(bs, vr_ctl, put_into_srfs);
1018
1019         serial_putc('H');
1020         program_async_controller(bs);
1021
1022 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
1023         serial_putc('I');
1024         /* Tell the bootrom where our entry point is so that it knows
1025          * where to jump to when finishing processing the LDR.  This
1026          * allows us to avoid small jump blocks in the LDR, and also
1027          * works around anomaly 05000389 (init address in external
1028          * memory causes bootrom to trigger external addressing IVHW).
1029          */
1030         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1031                 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
1032 #endif
1033
1034         serial_putc('>');
1035         serial_putc('\n');
1036
1037         serial_deinit();
1038 }