arch/blackfin/include/asm/cplb.h

   1 /*
   2  * cplb.h - defines for managing CPLB tables
   3  *
   4  * Copyright (c) 2002-2007 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __ASM_BLACKFIN_CPLB_H__
  10 #define __ASM_BLACKFIN_CPLB_H__
  11
  12 #include <asm/mach-common/bits/mpu.h>
  13
  14 #define CPLB_ENABLE_ICACHE_P    0
  15 #define CPLB_ENABLE_DCACHE_P    1
  16 #define CPLB_ENABLE_DCACHE2_P   2
  17 #define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
  18 #define CPLB_ENABLE_ICPLBS_P    4
  19 #define CPLB_ENABLE_DCPLBS_P    5
  20
  21 #define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
  22 #define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
  23 #define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
  24 #define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
  25 #define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
  26 #define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
  27 #define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
  28                                 CPLB_ENABLE_ICPLBS | \
  29                                 CPLB_ENABLE_DCPLBS
  30
  31 #define CPLB_RELOADED           0x0000
  32 #define CPLB_NO_UNLOCKED        0x0001
  33 #define CPLB_NO_ADDR_MATCH      0x0002
  34 #define CPLB_PROT_VIOL          0x0003
  35
  36 #define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
  37 #define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
  38
  39 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
  40
  41 #define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
  42 #define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
  43 #define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
  44 #define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
  45 #define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
  46 #define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
  47
  48 /* Data Attibutes*/
  49 #if defined(__ADSPBF60x__)
  50 #define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
  51                                 CPLB_USER_RD | CPLB_VALID)
  52 #else
  53 #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
  54                                 CPLB_USER_RD | CPLB_VALID)
  55 #endif
  56 #define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  57 #define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  58 #define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
  59
  60 #if ANOMALY_05000158
  61 # define ANOMALY_05000158_WORKAROUND 0x200
  62 #else
  63 # define ANOMALY_05000158_WORKAROUND 0
  64 #endif
  65
  66 #ifdef CONFIG_DCACHE_WB         /*Write Back Policy */
  67 #if defined(__ADSPBF60x__)
  68 #define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
  69                                 CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
  70                                 CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  71 #else
  72 #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
  73                                 CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
  74                                 CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  75 #endif
  76 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  77 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
  78 #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  79 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  80
  81 #else                           /*Write Through */
  82 #if defined(__ADSPBF60x__)
  83 #define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
  84                                 CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
  85                                 CPLB_USER_WR | CPLB_VALID | \
  86                                 ANOMALY_05000158_WORKAROUND)
  87 #else
  88 #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
  89                                 CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
  90                                 CPLB_USER_WR | CPLB_VALID | \
  91                                 ANOMALY_05000158_WORKAROUND)
  92 #endif
  93 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  94 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
  95 #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  96 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  97 #endif
  98
  99 #endif                          /* _CPLB_H */