arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  25         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  26         u32 total_gb_size_per_controller;
  27         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  28         int csn = -1;
  29 #endif
  30
  31         switch (ctrl_num) {
  32         case 0:
  33                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  34                 break;
  35         case 1:
  36                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  37                 break;
  38         default:
  39                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  40                 return;
  41         }
  42
  43         out_be32(&ddr->eor, regs->ddr_eor);
  44
  45 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  46         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  47                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  48                 cs_ea = regs->cs[i].bnds & 0xfff;
  49                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  50                         csn = i;
  51                         csn_bnds_backup = regs->cs[i].bnds;
  52                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  53                         *csn_bnds_t = regs->cs[i].bnds ^ 0x0F000F00;
  54                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  55                                 "change it to 0x%x\n",
  56                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  57                         break;
  58                 }
  59         }
  60 #endif
  61         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  62                 if (i == 0) {
  63                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  64                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  65                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  66
  67                 } else if (i == 1) {
  68                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  69                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  70                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  71
  72                 } else if (i == 2) {
  73                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  74                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  75                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  76
  77                 } else if (i == 3) {
  78                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  79                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  80                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  81                 }
  82         }
  83
  84         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  85         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  86         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  87         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  88         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  89         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  90         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  91         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  92         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  93         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  94         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  95         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  96         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  97         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  98         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  99         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 100         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 101         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 102         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 103
 104         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 105         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 106         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 107         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 108         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 109         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 110         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 111         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 112         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 113         out_be32(&ddr->err_disable, regs->err_disable);
 114         out_be32(&ddr->err_int_en, regs->err_int_en);
 115         for (i = 0; i < 32; i++)
 116                 out_be32(&ddr->debug[i], regs->debug[i]);
 117
 118 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 119         out_be32(&ddr->debug[12], 0x00000015);
 120         out_be32(&ddr->debug[21], 0x24000000);
 121 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 122
 123         /* Set, but do not enable the memory */
 124         temp_sdram_cfg = regs->ddr_sdram_cfg;
 125         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 126         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 127 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 128         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 129                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 130                 out_be32(&ddr->debug[2], 0x00000400);
 131                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 132                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 133                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 134                 out_be32(&ddr->mtcr, 0);
 135                 out_be32(&ddr->debug[12], 0x00000015);
 136                 out_be32(&ddr->debug[21], 0x24000000);
 137                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 138                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 139
 140                 asm volatile("sync;isync");
 141                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 142                         ;
 143
 144                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 145                 case 0x00000000:
 146                         out_be32(&ddr->sdram_md_cntl,
 147                                 MD_CNTL_MD_EN           |
 148                                 MD_CNTL_CS_SEL_CS0_CS1  |
 149                                 0x04000000              |
 150                                 MD_CNTL_WRCW            |
 151                                 MD_CNTL_MD_VALUE(0x02));
 152                         break;
 153                 case 0x00100000:
 154                         out_be32(&ddr->sdram_md_cntl,
 155                                 MD_CNTL_MD_EN           |
 156                                 MD_CNTL_CS_SEL_CS0_CS1  |
 157                                 0x04000000              |
 158                                 MD_CNTL_WRCW            |
 159                                 MD_CNTL_MD_VALUE(0x0a));
 160                         break;
 161                 case 0x00200000:
 162                         out_be32(&ddr->sdram_md_cntl,
 163                                 MD_CNTL_MD_EN           |
 164                                 MD_CNTL_CS_SEL_CS0_CS1  |
 165                                 0x04000000              |
 166                                 MD_CNTL_WRCW            |
 167                                 MD_CNTL_MD_VALUE(0x12));
 168                         break;
 169                 case 0x00300000:
 170                         out_be32(&ddr->sdram_md_cntl,
 171                                 MD_CNTL_MD_EN           |
 172                                 MD_CNTL_CS_SEL_CS0_CS1  |
 173                                 0x04000000              |
 174                                 MD_CNTL_WRCW            |
 175                                 MD_CNTL_MD_VALUE(0x1a));
 176                         break;
 177                 default:
 178                         out_be32(&ddr->sdram_md_cntl,
 179                                 MD_CNTL_MD_EN           |
 180                                 MD_CNTL_CS_SEL_CS0_CS1  |
 181                                 0x04000000              |
 182                                 MD_CNTL_WRCW            |
 183                                 MD_CNTL_MD_VALUE(0x02));
 184                         printf("Unsupported RC10\n");
 185                         break;
 186                 }
 187
 188                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 189                         ;
 190                 udelay(6);
 191                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 192                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 193                 out_be32(&ddr->debug[2], 0x0);
 194                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 195                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 196                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 197                 out_be32(&ddr->debug[12], 0x0);
 198                 out_be32(&ddr->debug[21], 0x0);
 199                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 200
 201         }
 202 #endif
 203         /*
 204          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 205          * when operatiing in 32-bit bus mode with 4-beat bursts,
 206          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 207          */
 208 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 209         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 210             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 211                 /* set DEBUG_1[31] */
 212                 setbits_be32(&ddr->debug[0], 1);
 213         }
 214 #endif
 215 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 216         /*
 217          * This is the combined workaround for DDR111 and DDR134
 218          * following the published errata for MPC8572
 219          */
 220
 221         /* 1. Set EEBACR[3] */
 222         setbits_be32(&ecm->eebacr, 0x10000000);
 223         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 224
 225         /* 2. Set DINIT in SDRAM_CFG_2*/
 226         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 227         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 228                 in_be32(&ddr->sdram_cfg_2));
 229
 230         /* 3. Set DEBUG_3[21] */
 231         setbits_be32(&ddr->debug[2], 0x400);
 232         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 233
 234 #endif  /* part 1 of the workaound */
 235
 236         /*
 237          * 500 painful micro-seconds must elapse between
 238          * the DDR clock setup and the DDR config enable.
 239          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 240          * we choose the max, that is 500 us for all of case.
 241          */
 242         udelay(500);
 243         asm volatile("sync;isync");
 244
 245         /* Let the controller go */
 246         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 247         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 248         asm volatile("sync;isync");
 249
 250         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 251         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 252                 udelay(10000);          /* throttle polling rate */
 253
 254 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 255         /* continue this workaround */
 256
 257         /* 4. Clear DEBUG3[21] */
 258         clrbits_be32(&ddr->debug[2], 0x400);
 259         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 260
 261         /* DDR134 workaround starts */
 262         /* A: Clear sdram_cfg_2[odt_cfg] */
 263         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 264         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 265                 in_be32(&ddr->sdram_cfg_2));
 266
 267         /* B: Set DEBUG1[15] */
 268         setbits_be32(&ddr->debug[0], 0x10000);
 269         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 270
 271         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 272         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 273         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 274                 in_be32(&ddr->timing_cfg_2));
 275
 276         /* D: Set D6 to 0x9f9f9f9f */
 277         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 278         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 279
 280         /* E: Set D7 to 0x9f9f9f9f */
 281         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 282         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 283
 284         /* F: Set D2[20] */
 285         setbits_be32(&ddr->debug[1], 0x800);
 286         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 287
 288         /* G: Poll on D2[20] until cleared */
 289         while (in_be32(&ddr->debug[1]) & 0x800)
 290                 udelay(10000);          /* throttle polling rate */
 291
 292         /* H: Clear D1[15] */
 293         clrbits_be32(&ddr->debug[0], 0x10000);
 294         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 295
 296         /* I: Set sdram_cfg_2[odt_cfg] */
 297         setbits_be32(&ddr->sdram_cfg_2,
 298                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 299         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 300
 301         /* Continuing with the DDR111 workaround */
 302         /* 5. Set D2[21] */
 303         setbits_be32(&ddr->debug[1], 0x400);
 304         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 305
 306         /* 6. Poll D2[21] until its cleared */
 307         while (in_be32(&ddr->debug[1]) & 0x400)
 308                 udelay(10000);          /* throttle polling rate */
 309
 310         /* 7. Wait for 400ms/GB */
 311         total_gb_size_per_controller = 0;
 312         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 313                 total_gb_size_per_controller +=
 314                                 ((regs->cs[i].bnds & 0xFFFF) >> 6)
 315                                 - (regs->cs[i].bnds >> 22) + 1;
 316         }
 317         if (in_be32(&ddr->sdram_cfg) & 0x80000)
 318                 total_gb_size_per_controller <<= 1;
 319         debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
 320         udelay(total_gb_size_per_controller * 400000);
 321
 322         /* 8. Set sdram_cfg_2[dinit] if options requires */
 323         setbits_be32(&ddr->sdram_cfg_2,
 324                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 325         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 326
 327         /* 9. Poll until dinit is cleared */
 328         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 329                 udelay(10000);
 330
 331         /* 10. Clear EEBACR[3] */
 332         clrbits_be32(&ecm->eebacr, 10000000);
 333         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 334
 335         if (csn != -1) {
 336                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 337                 *csn_bnds_t = csn_bnds_backup;
 338                 debug("Change cs%d_bnds back to 0x%08x\n",
 339                         csn, regs->cs[csn].bnds);
 340                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 341                 switch (csn) {
 342                 case 0:
 343                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 344                         break;
 345                 case 1:
 346                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 347                         break;
 348                 case 2:
 349                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 350                         break;
 351                 case 3:
 352                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 353                         break;
 354                 }
 355                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 356         }
 357 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 358 }