arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC83xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC85xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  25 #elif defined(CONFIG_MPC86xx)
  26         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  27 #else
  28         #error "Undefined _DDR_ADDR"
  29 #endif
  30
  31 u32 fsl_ddr_get_version(void)
  32 {
  33         ccsr_ddr_t *ddr;
  34         u32 ver_major_minor_errata;
  35
  36         ddr = (void *)_DDR_ADDR;
  37         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  38         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  39
  40         return ver_major_minor_errata;
  41 }
  42
  43 unsigned int picos_to_mclk(unsigned int picos);
  44
  45 /*
  46  * Determine Rtt value.
  47  *
  48  * This should likely be either board or controller specific.
  49  *
  50  * Rtt(nominal) - DDR2:
  51  *      0 = Rtt disabled
  52  *      1 = 75 ohm
  53  *      2 = 150 ohm
  54  *      3 = 50 ohm
  55  * Rtt(nominal) - DDR3:
  56  *      0 = Rtt disabled
  57  *      1 = 60 ohm
  58  *      2 = 120 ohm
  59  *      3 = 40 ohm
  60  *      4 = 20 ohm
  61  *      5 = 30 ohm
  62  *
  63  * FIXME: Apparently 8641 needs a value of 2
  64  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  65  *
  66  * FIXME: There was some effort down this line earlier:
  67  *
  68  *      unsigned int i;
  69  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  70  *              if (popts->dimmslot[i].num_valid_cs
  71  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  72  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  73  *                      rtt = 2;
  74  *                      break;
  75  *              }
  76  *      }
  77  */
  78 static inline int fsl_ddr_get_rtt(void)
  79 {
  80         int rtt;
  81
  82 #if defined(CONFIG_FSL_DDR1)
  83         rtt = 0;
  84 #elif defined(CONFIG_FSL_DDR2)
  85         rtt = 3;
  86 #else
  87         rtt = 0;
  88 #endif
  89
  90         return rtt;
  91 }
  92
  93 /*
  94  * compute the CAS write latency according to DDR3 spec
  95  * CWL = 5 if tCK >= 2.5ns
  96  *       6 if 2.5ns > tCK >= 1.875ns
  97  *       7 if 1.875ns > tCK >= 1.5ns
  98  *       8 if 1.5ns > tCK >= 1.25ns
  99  *       9 if 1.25ns > tCK >= 1.07ns
 100  *       10 if 1.07ns > tCK >= 0.935ns
 101  *       11 if 0.935ns > tCK >= 0.833ns
 102  *       12 if 0.833ns > tCK >= 0.75ns
 103  */
 104 static inline unsigned int compute_cas_write_latency(void)
 105 {
 106         unsigned int cwl;
 107         const unsigned int mclk_ps = get_memory_clk_period_ps();
 108
 109         if (mclk_ps >= 2500)
 110                 cwl = 5;
 111         else if (mclk_ps >= 1875)
 112                 cwl = 6;
 113         else if (mclk_ps >= 1500)
 114                 cwl = 7;
 115         else if (mclk_ps >= 1250)
 116                 cwl = 8;
 117         else if (mclk_ps >= 1070)
 118                 cwl = 9;
 119         else if (mclk_ps >= 935)
 120                 cwl = 10;
 121         else if (mclk_ps >= 833)
 122                 cwl = 11;
 123         else if (mclk_ps >= 750)
 124                 cwl = 12;
 125         else {
 126                 cwl = 12;
 127                 printf("Warning: CWL is out of range\n");
 128         }
 129         return cwl;
 130 }
 131
 132 /* Chip Select Configuration (CSn_CONFIG) */
 133 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 134                                const memctl_options_t *popts,
 135                                const dimm_params_t *dimm_params)
 136 {
 137         unsigned int cs_n_en = 0; /* Chip Select enable */
 138         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 139         unsigned int intlv_ctl = 0; /* Interleaving control */
 140         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 141         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 142         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 143         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 144         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 145         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 146         int go_config = 0;
 147
 148         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 149         switch (i) {
 150         case 0:
 151                 if (dimm_params[dimm_number].n_ranks > 0) {
 152                         go_config = 1;
 153                         /* These fields only available in CS0_CONFIG */
 154                         intlv_en = popts->memctl_interleaving;
 155                         intlv_ctl = popts->memctl_interleaving_mode;
 156                 }
 157                 break;
 158         case 1:
 159                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 160                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 161                         go_config = 1;
 162                 break;
 163         case 2:
 164                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 165                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 166                         go_config = 1;
 167                 break;
 168         case 3:
 169                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 170                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 171                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 172                         go_config = 1;
 173                 break;
 174         default:
 175                 break;
 176         }
 177         if (go_config) {
 178                 unsigned int n_banks_per_sdram_device;
 179                 cs_n_en = 1;
 180                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 181                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 182                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 183                 n_banks_per_sdram_device
 184                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 185                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 186                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 187                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 188         }
 189         ddr->cs[i].config = (0
 190                 | ((cs_n_en & 0x1) << 31)
 191                 | ((intlv_en & 0x3) << 29)
 192                 | ((intlv_ctl & 0xf) << 24)
 193                 | ((ap_n_en & 0x1) << 23)
 194
 195                 /* XXX: some implementation only have 1 bit starting at left */
 196                 | ((odt_rd_cfg & 0x7) << 20)
 197
 198                 /* XXX: Some implementation only have 1 bit starting at left */
 199                 | ((odt_wr_cfg & 0x7) << 16)
 200
 201                 | ((ba_bits_cs_n & 0x3) << 14)
 202                 | ((row_bits_cs_n & 0x7) << 8)
 203                 | ((col_bits_cs_n & 0x7) << 0)
 204                 );
 205         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 206 }
 207
 208 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 209 /* FIXME: 8572 */
 210 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 211 {
 212         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 213
 214         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 215         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 216 }
 217
 218 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 219
 220 #if !defined(CONFIG_FSL_DDR1)
 221 /*
 222  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 223  *
 224  * Avoid writing for DDR I.  The new PQ38 DDR controller
 225  * dreams up non-zero default values to be backwards compatible.
 226  */
 227 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 228                                 const memctl_options_t *popts)
 229 {
 230         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 231         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 232         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 233         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 234         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 235
 236         /* Active powerdown exit timing (tXARD and tXARDS). */
 237         unsigned char act_pd_exit_mclk;
 238         /* Precharge powerdown exit timing (tXP). */
 239         unsigned char pre_pd_exit_mclk;
 240         /* ODT powerdown exit timing (tAXPD). */
 241         unsigned char taxpd_mclk;
 242         /* Mode register set cycle time (tMRD). */
 243         unsigned char tmrd_mclk;
 244
 245 #ifdef CONFIG_FSL_DDR3
 246         /*
 247          * (tXARD and tXARDS). Empirical?
 248          * The DDR3 spec has not tXARD,
 249          * we use the tXP instead of it.
 250          * tXP=max(3nCK, 7.5ns) for DDR3.
 251          * spec has not the tAXPD, we use
 252          * tAXPD=1, need design to confirm.
 253          */
 254         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 255         unsigned int data_rate = get_ddr_freq(0);
 256         tmrd_mclk = 4;
 257         /* set the turnaround time */
 258         trwt_mclk = 1;
 259         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 260                 twrt_mclk = 1;
 261
 262         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 263                 act_pd_exit_mclk = 1;
 264                 pre_pd_exit_mclk = 1;
 265                 taxpd_mclk = 1;
 266         } else {
 267                 /* act_pd_exit_mclk = tXARD, see above */
 268                 act_pd_exit_mclk = picos_to_mclk(tXP);
 269                 /* Mode register MR0[A12] is '1' - fast exit */
 270                 pre_pd_exit_mclk = act_pd_exit_mclk;
 271                 taxpd_mclk = 1;
 272         }
 273 #else /* CONFIG_FSL_DDR2 */
 274         /*
 275          * (tXARD and tXARDS). Empirical?
 276          * tXARD = 2 for DDR2
 277          * tXP=2
 278          * tAXPD=8
 279          */
 280         act_pd_exit_mclk = 2;
 281         pre_pd_exit_mclk = 2;
 282         taxpd_mclk = 8;
 283         tmrd_mclk = 2;
 284 #endif
 285
 286         if (popts->trwt_override)
 287                 trwt_mclk = popts->trwt;
 288
 289         ddr->timing_cfg_0 = (0
 290                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 291                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 292                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 293                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 294                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 295                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 296                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 297                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 298                 );
 299         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 300 }
 301 #endif  /* defined(CONFIG_FSL_DDR2) */
 302
 303 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 304 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 305                                const common_timing_params_t *common_dimm,
 306                                unsigned int cas_latency)
 307 {
 308         /* Extended Activate to precharge interval (tRAS) */
 309         unsigned int ext_acttopre = 0;
 310         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 311         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 312         unsigned int cntl_adj = 0; /* Control Adjust */
 313
 314         /* If the tRAS > 19 MCLK, we use the ext mode */
 315         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 316                 ext_acttopre = 1;
 317
 318         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 319
 320         /* If the CAS latency more than 8, use the ext mode */
 321         if (cas_latency > 8)
 322                 ext_caslat = 1;
 323
 324         ddr->timing_cfg_3 = (0
 325                 | ((ext_acttopre & 0x1) << 24)
 326                 | ((ext_refrec & 0xF) << 16)
 327                 | ((ext_caslat & 0x1) << 12)
 328                 | ((cntl_adj & 0x7) << 0)
 329                 );
 330         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 331 }
 332
 333 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 334 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 335                                const memctl_options_t *popts,
 336                                const common_timing_params_t *common_dimm,
 337                                unsigned int cas_latency)
 338 {
 339         /* Precharge-to-activate interval (tRP) */
 340         unsigned char pretoact_mclk;
 341         /* Activate to precharge interval (tRAS) */
 342         unsigned char acttopre_mclk;
 343         /*  Activate to read/write interval (tRCD) */
 344         unsigned char acttorw_mclk;
 345         /* CASLAT */
 346         unsigned char caslat_ctrl;
 347         /*  Refresh recovery time (tRFC) ; trfc_low */
 348         unsigned char refrec_ctrl;
 349         /* Last data to precharge minimum interval (tWR) */
 350         unsigned char wrrec_mclk;
 351         /* Activate-to-activate interval (tRRD) */
 352         unsigned char acttoact_mclk;
 353         /* Last write data pair to read command issue interval (tWTR) */
 354         unsigned char wrtord_mclk;
 355         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 356         static const u8 wrrec_table[] = {
 357                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 358
 359         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 360         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 361         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 362
 363         /*
 364          * Translate CAS Latency to a DDR controller field value:
 365          *
 366          *      CAS Lat DDR I   DDR II  Ctrl
 367          *      Clocks  SPD Bit SPD Bit Value
 368          *      ------- ------- ------- -----
 369          *      1.0     0               0001
 370          *      1.5     1               0010
 371          *      2.0     2       2       0011
 372          *      2.5     3               0100
 373          *      3.0     4       3       0101
 374          *      3.5     5               0110
 375          *      4.0             4       0111
 376          *      4.5                     1000
 377          *      5.0             5       1001
 378          */
 379 #if defined(CONFIG_FSL_DDR1)
 380         caslat_ctrl = (cas_latency + 1) & 0x07;
 381 #elif defined(CONFIG_FSL_DDR2)
 382         caslat_ctrl = 2 * cas_latency - 1;
 383 #else
 384         /*
 385          * if the CAS latency more than 8 cycle,
 386          * we need set extend bit for it at
 387          * TIMING_CFG_3[EXT_CASLAT]
 388          */
 389         if (cas_latency > 8)
 390                 cas_latency -= 8;
 391         caslat_ctrl = 2 * cas_latency - 1;
 392 #endif
 393
 394         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 395         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 396
 397         wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 398         if (popts->OTF_burst_chop_en)
 399                 wrrec_mclk += 2;
 400
 401         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 402         /*
 403          * JEDEC has min requirement for tRRD
 404          */
 405 #if defined(CONFIG_FSL_DDR3)
 406         if (acttoact_mclk < 4)
 407                 acttoact_mclk = 4;
 408 #endif
 409         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 410         /*
 411          * JEDEC has some min requirements for tWTR
 412          */
 413 #if defined(CONFIG_FSL_DDR2)
 414         if (wrtord_mclk < 2)
 415                 wrtord_mclk = 2;
 416 #elif defined(CONFIG_FSL_DDR3)
 417         if (wrtord_mclk < 4)
 418                 wrtord_mclk = 4;
 419 #endif
 420         if (popts->OTF_burst_chop_en)
 421                 wrtord_mclk += 2;
 422
 423         ddr->timing_cfg_1 = (0
 424                 | ((pretoact_mclk & 0x0F) << 28)
 425                 | ((acttopre_mclk & 0x0F) << 24)
 426                 | ((acttorw_mclk & 0xF) << 20)
 427                 | ((caslat_ctrl & 0xF) << 16)
 428                 | ((refrec_ctrl & 0xF) << 12)
 429                 | ((wrrec_mclk & 0x0F) << 8)
 430                 | ((acttoact_mclk & 0x07) << 4)
 431                 | ((wrtord_mclk & 0x07) << 0)
 432                 );
 433         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 434 }
 435
 436 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 437 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 438                                const memctl_options_t *popts,
 439                                const common_timing_params_t *common_dimm,
 440                                unsigned int cas_latency,
 441                                unsigned int additive_latency)
 442 {
 443         /* Additive latency */
 444         unsigned char add_lat_mclk;
 445         /* CAS-to-preamble override */
 446         unsigned short cpo;
 447         /* Write latency */
 448         unsigned char wr_lat;
 449         /*  Read to precharge (tRTP) */
 450         unsigned char rd_to_pre;
 451         /* Write command to write data strobe timing adjustment */
 452         unsigned char wr_data_delay;
 453         /* Minimum CKE pulse width (tCKE) */
 454         unsigned char cke_pls;
 455         /* Window for four activates (tFAW) */
 456         unsigned short four_act;
 457
 458         /* FIXME add check that this must be less than acttorw_mclk */
 459         add_lat_mclk = additive_latency;
 460         cpo = popts->cpo_override;
 461
 462 #if defined(CONFIG_FSL_DDR1)
 463         /*
 464          * This is a lie.  It should really be 1, but if it is
 465          * set to 1, bits overlap into the old controller's
 466          * otherwise unused ACSM field.  If we leave it 0, then
 467          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 468          */
 469         wr_lat = 0;
 470 #elif defined(CONFIG_FSL_DDR2)
 471         wr_lat = cas_latency - 1;
 472 #else
 473         wr_lat = compute_cas_write_latency();
 474 #endif
 475
 476         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 477         /*
 478          * JEDEC has some min requirements for tRTP
 479          */
 480 #if defined(CONFIG_FSL_DDR2)
 481         if (rd_to_pre  < 2)
 482                 rd_to_pre  = 2;
 483 #elif defined(CONFIG_FSL_DDR3)
 484         if (rd_to_pre < 4)
 485                 rd_to_pre = 4;
 486 #endif
 487         if (additive_latency)
 488                 rd_to_pre += additive_latency;
 489         if (popts->OTF_burst_chop_en)
 490                 rd_to_pre += 2; /* according to UM */
 491
 492         wr_data_delay = popts->write_data_delay;
 493         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 494         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 495
 496         ddr->timing_cfg_2 = (0
 497                 | ((add_lat_mclk & 0xf) << 28)
 498                 | ((cpo & 0x1f) << 23)
 499                 | ((wr_lat & 0xf) << 19)
 500                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 501                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 502                 | ((cke_pls & 0x7) << 6)
 503                 | ((four_act & 0x3f) << 0)
 504                 );
 505         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 506 }
 507
 508 /* DDR SDRAM Register Control Word */
 509 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 510                                const memctl_options_t *popts,
 511                                const common_timing_params_t *common_dimm)
 512 {
 513         if (common_dimm->all_DIMMs_registered
 514                 && !common_dimm->all_DIMMs_unbuffered) {
 515                 if (popts->rcw_override) {
 516                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 517                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 518                 } else {
 519                         ddr->ddr_sdram_rcw_1 =
 520                                 common_dimm->rcw[0] << 28 | \
 521                                 common_dimm->rcw[1] << 24 | \
 522                                 common_dimm->rcw[2] << 20 | \
 523                                 common_dimm->rcw[3] << 16 | \
 524                                 common_dimm->rcw[4] << 12 | \
 525                                 common_dimm->rcw[5] << 8 | \
 526                                 common_dimm->rcw[6] << 4 | \
 527                                 common_dimm->rcw[7];
 528                         ddr->ddr_sdram_rcw_2 =
 529                                 common_dimm->rcw[8] << 28 | \
 530                                 common_dimm->rcw[9] << 24 | \
 531                                 common_dimm->rcw[10] << 20 | \
 532                                 common_dimm->rcw[11] << 16 | \
 533                                 common_dimm->rcw[12] << 12 | \
 534                                 common_dimm->rcw[13] << 8 | \
 535                                 common_dimm->rcw[14] << 4 | \
 536                                 common_dimm->rcw[15];
 537                 }
 538                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 539                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 540         }
 541 }
 542
 543 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 544 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 545                                const memctl_options_t *popts,
 546                                const common_timing_params_t *common_dimm)
 547 {
 548         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 549         unsigned int sren;              /* Self refresh enable (during sleep) */
 550         unsigned int ecc_en;            /* ECC enable. */
 551         unsigned int rd_en;             /* Registered DIMM enable */
 552         unsigned int sdram_type;        /* Type of SDRAM */
 553         unsigned int dyn_pwr;           /* Dynamic power management mode */
 554         unsigned int dbw;               /* DRAM dta bus width */
 555         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 556         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 557         unsigned int threeT_en;         /* Enable 3T timing */
 558         unsigned int twoT_en;           /* Enable 2T timing */
 559         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 560         unsigned int x32_en = 0;        /* x32 enable */
 561         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 562         unsigned int hse;               /* Global half strength override */
 563         unsigned int mem_halt = 0;      /* memory controller halt */
 564         unsigned int bi = 0;            /* Bypass initialization */
 565
 566         mem_en = 1;
 567         sren = popts->self_refresh_in_sleep;
 568         if (common_dimm->all_DIMMs_ECC_capable) {
 569                 /* Allow setting of ECC only if all DIMMs are ECC. */
 570                 ecc_en = popts->ECC_mode;
 571         } else {
 572                 ecc_en = 0;
 573         }
 574
 575         if (common_dimm->all_DIMMs_registered
 576                 && !common_dimm->all_DIMMs_unbuffered) {
 577                 rd_en = 1;
 578                 twoT_en = 0;
 579         } else {
 580                 rd_en = 0;
 581                 twoT_en = popts->twoT_en;
 582         }
 583
 584         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 585
 586         dyn_pwr = popts->dynamic_power;
 587         dbw = popts->data_bus_width;
 588         /* 8-beat burst enable DDR-III case
 589          * we must clear it when use the on-the-fly mode,
 590          * must set it when use the 32-bits bus mode.
 591          */
 592         if (sdram_type == SDRAM_TYPE_DDR3) {
 593                 if (popts->burst_length == DDR_BL8)
 594                         eight_be = 1;
 595                 if (popts->burst_length == DDR_OTF)
 596                         eight_be = 0;
 597                 if (dbw == 0x1)
 598                         eight_be = 1;
 599         }
 600
 601         threeT_en = popts->threeT_en;
 602         ba_intlv_ctl = popts->ba_intlv_ctl;
 603         hse = popts->half_strength_driver_enable;
 604
 605         ddr->ddr_sdram_cfg = (0
 606                         | ((mem_en & 0x1) << 31)
 607                         | ((sren & 0x1) << 30)
 608                         | ((ecc_en & 0x1) << 29)
 609                         | ((rd_en & 0x1) << 28)
 610                         | ((sdram_type & 0x7) << 24)
 611                         | ((dyn_pwr & 0x1) << 21)
 612                         | ((dbw & 0x3) << 19)
 613                         | ((eight_be & 0x1) << 18)
 614                         | ((ncap & 0x1) << 17)
 615                         | ((threeT_en & 0x1) << 16)
 616                         | ((twoT_en & 0x1) << 15)
 617                         | ((ba_intlv_ctl & 0x7F) << 8)
 618                         | ((x32_en & 0x1) << 5)
 619                         | ((pchb8 & 0x1) << 4)
 620                         | ((hse & 0x1) << 3)
 621                         | ((mem_halt & 0x1) << 1)
 622                         | ((bi & 0x1) << 0)
 623                         );
 624         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 625 }
 626
 627 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 628 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 629                                const memctl_options_t *popts,
 630                                const unsigned int unq_mrs_en)
 631 {
 632         unsigned int frc_sr = 0;        /* Force self refresh */
 633         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 634         unsigned int dll_rst_dis;       /* DLL reset disable */
 635         unsigned int dqs_cfg;           /* DQS configuration */
 636         unsigned int odt_cfg = 0;       /* ODT configuration */
 637         unsigned int num_pr;            /* Number of posted refreshes */
 638         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 639         unsigned int ap_en;             /* Address Parity Enable */
 640         unsigned int d_init;            /* DRAM data initialization */
 641         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 642         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 643         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 644         int i;
 645
 646         dll_rst_dis = 1;        /* Make this configurable */
 647         dqs_cfg = popts->DQS_config;
 648         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 649                 if (popts->cs_local_opts[i].odt_rd_cfg
 650                         || popts->cs_local_opts[i].odt_wr_cfg) {
 651                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 652                         break;
 653                 }
 654         }
 655
 656         num_pr = 1;     /* Make this configurable */
 657
 658         /*
 659          * 8572 manual says
 660          *     {TIMING_CFG_1[PRETOACT]
 661          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 662          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 663          *      << DDR_SDRAM_INTERVAL[REFINT]
 664          */
 665 #if defined(CONFIG_FSL_DDR3)
 666         obc_cfg = popts->OTF_burst_chop_en;
 667 #else
 668         obc_cfg = 0;
 669 #endif
 670
 671         if (popts->registered_dimm_en) {
 672                 rcw_en = 1;
 673                 ap_en = popts->ap_en;
 674         } else {
 675                 ap_en = 0;
 676         }
 677
 678 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 679         /* Use the DDR controller to auto initialize memory. */
 680         d_init = popts->ECC_init_using_memctl;
 681         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 682         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 683 #else
 684         /* Memory will be initialized via DMA, or not at all. */
 685         d_init = 0;
 686 #endif
 687
 688 #if defined(CONFIG_FSL_DDR3)
 689         md_en = popts->mirrored_dimm;
 690 #endif
 691         qd_en = popts->quad_rank_present ? 1 : 0;
 692         ddr->ddr_sdram_cfg_2 = (0
 693                 | ((frc_sr & 0x1) << 31)
 694                 | ((sr_ie & 0x1) << 30)
 695                 | ((dll_rst_dis & 0x1) << 29)
 696                 | ((dqs_cfg & 0x3) << 26)
 697                 | ((odt_cfg & 0x3) << 21)
 698                 | ((num_pr & 0xf) << 12)
 699                 | (qd_en << 9)
 700                 | (unq_mrs_en << 8)
 701                 | ((obc_cfg & 0x1) << 6)
 702                 | ((ap_en & 0x1) << 5)
 703                 | ((d_init & 0x1) << 4)
 704                 | ((rcw_en & 0x1) << 2)
 705                 | ((md_en & 0x1) << 0)
 706                 );
 707         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 708 }
 709
 710 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 711 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 712                                 const memctl_options_t *popts,
 713                                 const unsigned int unq_mrs_en)
 714 {
 715         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 716         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 717
 718 #if defined(CONFIG_FSL_DDR3)
 719         int i;
 720         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 721         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 722         unsigned int asr = 0;   /* auto self-refresh disable */
 723         unsigned int cwl = compute_cas_write_latency() - 5;
 724         unsigned int pasr = 0;  /* partial array self refresh disable */
 725
 726         if (popts->rtt_override)
 727                 rtt_wr = popts->rtt_wr_override_value;
 728         else
 729                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 730         esdmode2 = (0
 731                 | ((rtt_wr & 0x3) << 9)
 732                 | ((srt & 0x1) << 7)
 733                 | ((asr & 0x1) << 6)
 734                 | ((cwl & 0x7) << 3)
 735                 | ((pasr & 0x7) << 0));
 736 #endif
 737         ddr->ddr_sdram_mode_2 = (0
 738                                  | ((esdmode2 & 0xFFFF) << 16)
 739                                  | ((esdmode3 & 0xFFFF) << 0)
 740                                  );
 741         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 742
 743 #ifdef CONFIG_FSL_DDR3
 744         if (unq_mrs_en) {       /* unique mode registers are supported */
 745                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 746                         if (popts->rtt_override)
 747                                 rtt_wr = popts->rtt_wr_override_value;
 748                         else
 749                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 750
 751                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 752                         esdmode2 |= (rtt_wr & 0x3) << 9;
 753                         switch (i) {
 754                         case 1:
 755                                 ddr->ddr_sdram_mode_4 = (0
 756                                         | ((esdmode2 & 0xFFFF) << 16)
 757                                         | ((esdmode3 & 0xFFFF) << 0)
 758                                         );
 759                                 break;
 760                         case 2:
 761                                 ddr->ddr_sdram_mode_6 = (0
 762                                         | ((esdmode2 & 0xFFFF) << 16)
 763                                         | ((esdmode3 & 0xFFFF) << 0)
 764                                         );
 765                                 break;
 766                         case 3:
 767                                 ddr->ddr_sdram_mode_8 = (0
 768                                         | ((esdmode2 & 0xFFFF) << 16)
 769                                         | ((esdmode3 & 0xFFFF) << 0)
 770                                         );
 771                                 break;
 772                         }
 773                 }
 774                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 775                         ddr->ddr_sdram_mode_4);
 776                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 777                         ddr->ddr_sdram_mode_6);
 778                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 779                         ddr->ddr_sdram_mode_8);
 780         }
 781 #endif
 782 }
 783
 784 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 785 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 786                                const memctl_options_t *popts,
 787                                const common_timing_params_t *common_dimm)
 788 {
 789         unsigned int refint;    /* Refresh interval */
 790         unsigned int bstopre;   /* Precharge interval */
 791
 792         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 793
 794         bstopre = popts->bstopre;
 795
 796         /* refint field used 0x3FFF in earlier controllers */
 797         ddr->ddr_sdram_interval = (0
 798                                    | ((refint & 0xFFFF) << 16)
 799                                    | ((bstopre & 0x3FFF) << 0)
 800                                    );
 801         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 802 }
 803
 804 #if defined(CONFIG_FSL_DDR3)
 805 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 806 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 807                                const memctl_options_t *popts,
 808                                const common_timing_params_t *common_dimm,
 809                                unsigned int cas_latency,
 810                                unsigned int additive_latency,
 811                                const unsigned int unq_mrs_en)
 812 {
 813         unsigned short esdmode;         /* Extended SDRAM mode */
 814         unsigned short sdmode;          /* SDRAM mode */
 815
 816         /* Mode Register - MR1 */
 817         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 818         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 819         unsigned int rtt;
 820         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 821         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 822         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 823         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 824                                                        1=Disable (Test/Debug) */
 825
 826         /* Mode Register - MR0 */
 827         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 828         unsigned int wr;        /* Write Recovery */
 829         unsigned int dll_rst;   /* DLL Reset */
 830         unsigned int mode;      /* Normal=0 or Test=1 */
 831         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 832         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 833         unsigned int bt;
 834         unsigned int bl;        /* BL: Burst Length */
 835
 836         unsigned int wr_mclk;
 837         /*
 838          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 839          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 840          * for this table
 841          */
 842         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 843
 844         const unsigned int mclk_ps = get_memory_clk_period_ps();
 845         int i;
 846
 847         if (popts->rtt_override)
 848                 rtt = popts->rtt_override_value;
 849         else
 850                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 851
 852         if (additive_latency == (cas_latency - 1))
 853                 al = 1;
 854         if (additive_latency == (cas_latency - 2))
 855                 al = 2;
 856
 857         if (popts->quad_rank_present)
 858                 dic = 1;        /* output driver impedance 240/7 ohm */
 859
 860         /*
 861          * The esdmode value will also be used for writing
 862          * MR1 during write leveling for DDR3, although the
 863          * bits specifically related to the write leveling
 864          * scheme will be handled automatically by the DDR
 865          * controller. so we set the wrlvl_en = 0 here.
 866          */
 867         esdmode = (0
 868                 | ((qoff & 0x1) << 12)
 869                 | ((tdqs_en & 0x1) << 11)
 870                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 871                 | ((wrlvl_en & 0x1) << 7)
 872                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 873                 | ((dic & 0x2) << 4)   /* DIC field is split */
 874                 | ((al & 0x3) << 3)
 875                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 876                 | ((dic & 0x1) << 1)   /* DIC field is split */
 877                 | ((dll_en & 0x1) << 0)
 878                 );
 879
 880         /*
 881          * DLL control for precharge PD
 882          * 0=slow exit DLL off (tXPDLL)
 883          * 1=fast exit DLL on (tXP)
 884          */
 885         dll_on = 1;
 886
 887         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 888         wr = wr_table[wr_mclk - 5];
 889
 890         dll_rst = 0;    /* dll no reset */
 891         mode = 0;       /* normal mode */
 892
 893         /* look up table to get the cas latency bits */
 894         if (cas_latency >= 5 && cas_latency <= 11) {
 895                 unsigned char cas_latency_table[7] = {
 896                         0x2,    /* 5 clocks */
 897                         0x4,    /* 6 clocks */
 898                         0x6,    /* 7 clocks */
 899                         0x8,    /* 8 clocks */
 900                         0xa,    /* 9 clocks */
 901                         0xc,    /* 10 clocks */
 902                         0xe     /* 11 clocks */
 903                 };
 904                 caslat = cas_latency_table[cas_latency - 5];
 905         }
 906         bt = 0; /* Nibble sequential */
 907
 908         switch (popts->burst_length) {
 909         case DDR_BL8:
 910                 bl = 0;
 911                 break;
 912         case DDR_OTF:
 913                 bl = 1;
 914                 break;
 915         case DDR_BC4:
 916                 bl = 2;
 917                 break;
 918         default:
 919                 printf("Error: invalid burst length of %u specified. "
 920                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 921                         popts->burst_length);
 922                 bl = 1;
 923                 break;
 924         }
 925
 926         sdmode = (0
 927                   | ((dll_on & 0x1) << 12)
 928                   | ((wr & 0x7) << 9)
 929                   | ((dll_rst & 0x1) << 8)
 930                   | ((mode & 0x1) << 7)
 931                   | (((caslat >> 1) & 0x7) << 4)
 932                   | ((bt & 0x1) << 3)
 933                   | ((bl & 0x3) << 0)
 934                   );
 935
 936         ddr->ddr_sdram_mode = (0
 937                                | ((esdmode & 0xFFFF) << 16)
 938                                | ((sdmode & 0xFFFF) << 0)
 939                                );
 940
 941         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 942
 943         if (unq_mrs_en) {       /* unique mode registers are supported */
 944                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 945                         if (popts->rtt_override)
 946                                 rtt = popts->rtt_override_value;
 947                         else
 948                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
 949
 950                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
 951                         esdmode |= (0
 952                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 953                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 954                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 955                                 );
 956                         switch (i) {
 957                         case 1:
 958                                 ddr->ddr_sdram_mode_3 = (0
 959                                        | ((esdmode & 0xFFFF) << 16)
 960                                        | ((sdmode & 0xFFFF) << 0)
 961                                        );
 962                                 break;
 963                         case 2:
 964                                 ddr->ddr_sdram_mode_5 = (0
 965                                        | ((esdmode & 0xFFFF) << 16)
 966                                        | ((sdmode & 0xFFFF) << 0)
 967                                        );
 968                                 break;
 969                         case 3:
 970                                 ddr->ddr_sdram_mode_7 = (0
 971                                        | ((esdmode & 0xFFFF) << 16)
 972                                        | ((sdmode & 0xFFFF) << 0)
 973                                        );
 974                                 break;
 975                         }
 976                 }
 977                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
 978                         ddr->ddr_sdram_mode_3);
 979                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 980                         ddr->ddr_sdram_mode_5);
 981                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 982                         ddr->ddr_sdram_mode_5);
 983         }
 984 }
 985
 986 #else /* !CONFIG_FSL_DDR3 */
 987
 988 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 989 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 990                                const memctl_options_t *popts,
 991                                const common_timing_params_t *common_dimm,
 992                                unsigned int cas_latency,
 993                                unsigned int additive_latency,
 994                                const unsigned int unq_mrs_en)
 995 {
 996         unsigned short esdmode;         /* Extended SDRAM mode */
 997         unsigned short sdmode;          /* SDRAM mode */
 998
 999         /*
1000          * FIXME: This ought to be pre-calculated in a
1001          * technology-specific routine,
1002          * e.g. compute_DDR2_mode_register(), and then the
1003          * sdmode and esdmode passed in as part of common_dimm.
1004          */
1005
1006         /* Extended Mode Register */
1007         unsigned int mrs = 0;           /* Mode Register Set */
1008         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1009         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1010         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1011         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1012                                            0x7=OCD default state */
1013         unsigned int rtt;
1014         unsigned int al;                /* Posted CAS# additive latency (AL) */
1015         unsigned int ods = 0;           /* Output Drive Strength:
1016                                                 0 = Full strength (18ohm)
1017                                                 1 = Reduced strength (4ohm) */
1018         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1019                                                        1=Disable (Test/Debug) */
1020
1021         /* Mode Register (MR) */
1022         unsigned int mr;        /* Mode Register Definition */
1023         unsigned int pd;        /* Power-Down Mode */
1024         unsigned int wr;        /* Write Recovery */
1025         unsigned int dll_res;   /* DLL Reset */
1026         unsigned int mode;      /* Normal=0 or Test=1 */
1027         unsigned int caslat = 0;/* CAS# latency */
1028         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1029         unsigned int bt;
1030         unsigned int bl;        /* BL: Burst Length */
1031
1032 #if defined(CONFIG_FSL_DDR2)
1033         const unsigned int mclk_ps = get_memory_clk_period_ps();
1034 #endif
1035         dqs_en = !popts->DQS_config;
1036         rtt = fsl_ddr_get_rtt();
1037
1038         al = additive_latency;
1039
1040         esdmode = (0
1041                 | ((mrs & 0x3) << 14)
1042                 | ((outputs & 0x1) << 12)
1043                 | ((rdqs_en & 0x1) << 11)
1044                 | ((dqs_en & 0x1) << 10)
1045                 | ((ocd & 0x7) << 7)
1046                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1047                 | ((al & 0x7) << 3)
1048                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1049                 | ((ods & 0x1) << 1)
1050                 | ((dll_en & 0x1) << 0)
1051                 );
1052
1053         mr = 0;          /* FIXME: CHECKME */
1054
1055         /*
1056          * 0 = Fast Exit (Normal)
1057          * 1 = Slow Exit (Low Power)
1058          */
1059         pd = 0;
1060
1061 #if defined(CONFIG_FSL_DDR1)
1062         wr = 0;       /* Historical */
1063 #elif defined(CONFIG_FSL_DDR2)
1064         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1065 #endif
1066         dll_res = 0;
1067         mode = 0;
1068
1069 #if defined(CONFIG_FSL_DDR1)
1070         if (1 <= cas_latency && cas_latency <= 4) {
1071                 unsigned char mode_caslat_table[4] = {
1072                         0x5,    /* 1.5 clocks */
1073                         0x2,    /* 2.0 clocks */
1074                         0x6,    /* 2.5 clocks */
1075                         0x3     /* 3.0 clocks */
1076                 };
1077                 caslat = mode_caslat_table[cas_latency - 1];
1078         } else {
1079                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1080         }
1081 #elif defined(CONFIG_FSL_DDR2)
1082         caslat = cas_latency;
1083 #endif
1084         bt = 0;
1085
1086         switch (popts->burst_length) {
1087         case DDR_BL4:
1088                 bl = 2;
1089                 break;
1090         case DDR_BL8:
1091                 bl = 3;
1092                 break;
1093         default:
1094                 printf("Error: invalid burst length of %u specified. "
1095                         " Defaulting to 4 beats.\n",
1096                         popts->burst_length);
1097                 bl = 2;
1098                 break;
1099         }
1100
1101         sdmode = (0
1102                   | ((mr & 0x3) << 14)
1103                   | ((pd & 0x1) << 12)
1104                   | ((wr & 0x7) << 9)
1105                   | ((dll_res & 0x1) << 8)
1106                   | ((mode & 0x1) << 7)
1107                   | ((caslat & 0x7) << 4)
1108                   | ((bt & 0x1) << 3)
1109                   | ((bl & 0x7) << 0)
1110                   );
1111
1112         ddr->ddr_sdram_mode = (0
1113                                | ((esdmode & 0xFFFF) << 16)
1114                                | ((sdmode & 0xFFFF) << 0)
1115                                );
1116         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1117 }
1118 #endif
1119
1120 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1121 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1122 {
1123         unsigned int init_value;        /* Initialization value */
1124
1125         init_value = 0xDEADBEEF;
1126         ddr->ddr_data_init = init_value;
1127 }
1128
1129 /*
1130  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1131  * The old controller on the 8540/60 doesn't have this register.
1132  * Hope it's OK to set it (to 0) anyway.
1133  */
1134 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1135                                          const memctl_options_t *popts)
1136 {
1137         unsigned int clk_adjust;        /* Clock adjust */
1138
1139         clk_adjust = popts->clk_adjust;
1140         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1141         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1142 }
1143
1144 /* DDR Initialization Address (DDR_INIT_ADDR) */
1145 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1146 {
1147         unsigned int init_addr = 0;     /* Initialization address */
1148
1149         ddr->ddr_init_addr = init_addr;
1150 }
1151
1152 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1153 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1154 {
1155         unsigned int uia = 0;   /* Use initialization address */
1156         unsigned int init_ext_addr = 0; /* Initialization address */
1157
1158         ddr->ddr_init_ext_addr = (0
1159                                   | ((uia & 0x1) << 31)
1160                                   | (init_ext_addr & 0xF)
1161                                   );
1162 }
1163
1164 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1165 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1166                                 const memctl_options_t *popts)
1167 {
1168         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1169         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1170         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1171         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1172         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1173
1174 #if defined(CONFIG_FSL_DDR3)
1175         if (popts->burst_length == DDR_BL8) {
1176                 /* We set BL/2 for fixed BL8 */
1177                 rrt = 0;        /* BL/2 clocks */
1178                 wwt = 0;        /* BL/2 clocks */
1179         } else {
1180                 /* We need to set BL/2 + 2 to BC4 and OTF */
1181                 rrt = 2;        /* BL/2 + 2 clocks */
1182                 wwt = 2;        /* BL/2 + 2 clocks */
1183         }
1184         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1185 #endif
1186         ddr->timing_cfg_4 = (0
1187                              | ((rwt & 0xf) << 28)
1188                              | ((wrt & 0xf) << 24)
1189                              | ((rrt & 0xf) << 20)
1190                              | ((wwt & 0xf) << 16)
1191                              | (dll_lock & 0x3)
1192                              );
1193         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1194 }
1195
1196 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1197 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1198 {
1199         unsigned int rodt_on = 0;       /* Read to ODT on */
1200         unsigned int rodt_off = 0;      /* Read to ODT off */
1201         unsigned int wodt_on = 0;       /* Write to ODT on */
1202         unsigned int wodt_off = 0;      /* Write to ODT off */
1203
1204 #if defined(CONFIG_FSL_DDR3)
1205         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1206         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1207         rodt_off = 4;   /*  4 clocks */
1208         wodt_on = 1;    /*  1 clocks */
1209         wodt_off = 4;   /*  4 clocks */
1210 #endif
1211
1212         ddr->timing_cfg_5 = (0
1213                              | ((rodt_on & 0x1f) << 24)
1214                              | ((rodt_off & 0x7) << 20)
1215                              | ((wodt_on & 0x1f) << 12)
1216                              | ((wodt_off & 0x7) << 8)
1217                              );
1218         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1219 }
1220
1221 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1222 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1223 {
1224         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1225         /* Normal Operation Full Calibration Time (tZQoper) */
1226         unsigned int zqoper = 0;
1227         /* Normal Operation Short Calibration Time (tZQCS) */
1228         unsigned int zqcs = 0;
1229
1230         if (zq_en) {
1231                 zqinit = 9;     /* 512 clocks */
1232                 zqoper = 8;     /* 256 clocks */
1233                 zqcs = 6;       /* 64 clocks */
1234         }
1235
1236         ddr->ddr_zq_cntl = (0
1237                             | ((zq_en & 0x1) << 31)
1238                             | ((zqinit & 0xF) << 24)
1239                             | ((zqoper & 0xF) << 16)
1240                             | ((zqcs & 0xF) << 8)
1241                             );
1242         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1243 }
1244
1245 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1246 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1247                                 const memctl_options_t *popts)
1248 {
1249         /*
1250          * First DQS pulse rising edge after margining mode
1251          * is programmed (tWL_MRD)
1252          */
1253         unsigned int wrlvl_mrd = 0;
1254         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1255         unsigned int wrlvl_odten = 0;
1256         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1257         unsigned int wrlvl_dqsen = 0;
1258         /* WRLVL_SMPL: Write leveling sample time */
1259         unsigned int wrlvl_smpl = 0;
1260         /* WRLVL_WLR: Write leveling repeition time */
1261         unsigned int wrlvl_wlr = 0;
1262         /* WRLVL_START: Write leveling start time */
1263         unsigned int wrlvl_start = 0;
1264
1265         /* suggest enable write leveling for DDR3 due to fly-by topology */
1266         if (wrlvl_en) {
1267                 /* tWL_MRD min = 40 nCK, we set it 64 */
1268                 wrlvl_mrd = 0x6;
1269                 /* tWL_ODTEN 128 */
1270                 wrlvl_odten = 0x7;
1271                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1272                 wrlvl_dqsen = 0x5;
1273                 /*
1274                  * Write leveling sample time at least need 6 clocks
1275                  * higher than tWLO to allow enough time for progagation
1276                  * delay and sampling the prime data bits.
1277                  */
1278                 wrlvl_smpl = 0xf;
1279                 /*
1280                  * Write leveling repetition time
1281                  * at least tWLO + 6 clocks clocks
1282                  * we set it 64
1283                  */
1284                 wrlvl_wlr = 0x6;
1285                 /*
1286                  * Write leveling start time
1287                  * The value use for the DQS_ADJUST for the first sample
1288                  * when write leveling is enabled. It probably needs to be
1289                  * overriden per platform.
1290                  */
1291                 wrlvl_start = 0x8;
1292                 /*
1293                  * Override the write leveling sample and start time
1294                  * according to specific board
1295                  */
1296                 if (popts->wrlvl_override) {
1297                         wrlvl_smpl = popts->wrlvl_sample;
1298                         wrlvl_start = popts->wrlvl_start;
1299                 }
1300         }
1301
1302         ddr->ddr_wrlvl_cntl = (0
1303                                | ((wrlvl_en & 0x1) << 31)
1304                                | ((wrlvl_mrd & 0x7) << 24)
1305                                | ((wrlvl_odten & 0x7) << 20)
1306                                | ((wrlvl_dqsen & 0x7) << 16)
1307                                | ((wrlvl_smpl & 0xf) << 12)
1308                                | ((wrlvl_wlr & 0x7) << 8)
1309                                | ((wrlvl_start & 0x1F) << 0)
1310                                );
1311         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1312 }
1313
1314 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1315 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1316 {
1317         /* Self Refresh Idle Threshold */
1318         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1319 }
1320
1321 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1322 {
1323         if (popts->addr_hash) {
1324                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1325                 puts("Address hashing enabled.\n");
1326         }
1327 }
1328
1329 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1330 {
1331         ddr->ddr_cdr1 = popts->ddr_cdr1;
1332         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1333 }
1334
1335 unsigned int
1336 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1337 {
1338         unsigned int res = 0;
1339
1340         /*
1341          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1342          * not set at the same time.
1343          */
1344         if (ddr->ddr_sdram_cfg & 0x10000000
1345             && ddr->ddr_sdram_cfg & 0x00008000) {
1346                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1347                                 " should not be set at the same time.\n");
1348                 res++;
1349         }
1350
1351         return res;
1352 }
1353
1354 unsigned int
1355 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1356                                fsl_ddr_cfg_regs_t *ddr,
1357                                const common_timing_params_t *common_dimm,
1358                                const dimm_params_t *dimm_params,
1359                                unsigned int dbw_cap_adj,
1360                                unsigned int size_only)
1361 {
1362         unsigned int i;
1363         unsigned int cas_latency;
1364         unsigned int additive_latency;
1365         unsigned int sr_it;
1366         unsigned int zq_en;
1367         unsigned int wrlvl_en;
1368         unsigned int ip_rev = 0;
1369         unsigned int unq_mrs_en = 0;
1370         int cs_en = 1;
1371
1372         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1373
1374         if (common_dimm == NULL) {
1375                 printf("Error: subset DIMM params struct null pointer\n");
1376                 return 1;
1377         }
1378
1379         /*
1380          * Process overrides first.
1381          *
1382          * FIXME: somehow add dereated caslat to this
1383          */
1384         cas_latency = (popts->cas_latency_override)
1385                 ? popts->cas_latency_override_value
1386                 : common_dimm->lowest_common_SPD_caslat;
1387
1388         additive_latency = (popts->additive_latency_override)
1389                 ? popts->additive_latency_override_value
1390                 : common_dimm->additive_latency;
1391
1392         sr_it = (popts->auto_self_refresh_en)
1393                 ? popts->sr_it
1394                 : 0;
1395         /* ZQ calibration */
1396         zq_en = (popts->zq_en) ? 1 : 0;
1397         /* write leveling */
1398         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1399
1400         /* Chip Select Memory Bounds (CSn_BNDS) */
1401         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1402                 unsigned long long ea = 0, sa = 0;
1403                 unsigned int cs_per_dimm
1404                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1405                 unsigned int dimm_number
1406                         = i / cs_per_dimm;
1407                 unsigned long long rank_density
1408                         = dimm_params[dimm_number].rank_density;
1409
1410                 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1411                         ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1412                         ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1413                         /*
1414                          * Don't set up boundaries for unused CS
1415                          * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1416                          * cs2 for cs0_cs1_cs2_cs3
1417                          * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1418                          * But we need to set the ODT_RD_CFG and
1419                          * ODT_WR_CFG for CS1_CONFIG here.
1420                          */
1421                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1422                         continue;
1423                 }
1424                 if (dimm_params[dimm_number].n_ranks == 0) {
1425                         debug("Skipping setup of CS%u "
1426                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1427                         continue;
1428                 }
1429                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1430                         /*
1431                          * This works superbank 2CS
1432                          * There are 2 or more memory controllers configured
1433                          * identically, memory is interleaved between them,
1434                          * and each controller uses rank interleaving within
1435                          * itself. Therefore the starting and ending address
1436                          * on each controller is twice the amount present on
1437                          * each controller. If any CS is not included in the
1438                          * interleaving, the memory on that CS is not accssible
1439                          * and the total memory size is reduced. The CS is also
1440                          * disabled.
1441                          */
1442                         unsigned long long ctlr_density = 0;
1443                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1444                         case FSL_DDR_CS0_CS1:
1445                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1446                                 ctlr_density = dimm_params[0].rank_density * 2;
1447                                 if (i > 1)
1448                                         cs_en = 0;
1449                                 break;
1450                         case FSL_DDR_CS2_CS3:
1451                                 ctlr_density = dimm_params[0].rank_density;
1452                                 if (i > 0)
1453                                         cs_en = 0;
1454                                 break;
1455                         case FSL_DDR_CS0_CS1_CS2_CS3:
1456                                 /*
1457                                  * The four CS interleaving should have been verified by
1458                                  * populate_memctl_options()
1459                                  */
1460                                 ctlr_density = dimm_params[0].rank_density * 4;
1461                                 break;
1462                         default:
1463                                 break;
1464                         }
1465                         ea = (CONFIG_NUM_DDR_CONTROLLERS *
1466                                 (ctlr_density >> dbw_cap_adj)) - 1;
1467                 }
1468                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1469                         /*
1470                          * If memory interleaving between controllers is NOT
1471                          * enabled, the starting address for each memory
1472                          * controller is distinct.  However, because rank
1473                          * interleaving is enabled, the starting and ending
1474                          * addresses of the total memory on that memory
1475                          * controller needs to be programmed into its
1476                          * respective CS0_BNDS.
1477                          */
1478                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1479                         case FSL_DDR_CS0_CS1_CS2_CS3:
1480                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1481                                  * needs to be set.
1482                                  */
1483                                 sa = common_dimm->base_address;
1484                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1485                                 break;
1486                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1487                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1488                                  * and CS2_CNDS need to be set.
1489                                  */
1490                                 if ((i == 2) && (dimm_number == 0)) {
1491                                         sa = dimm_params[dimm_number].base_address +
1492                                               2 * (rank_density >> dbw_cap_adj);
1493                                         ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1494                                 } else {
1495                                         sa = dimm_params[dimm_number].base_address;
1496                                         ea = sa + (2 * (rank_density >>
1497                                                 dbw_cap_adj)) - 1;
1498                                 }
1499                                 break;
1500                         case FSL_DDR_CS0_CS1:
1501                                 /* CS0+CS1 interleaving, CS0_CNDS needs
1502                                  * to be set
1503                                  */
1504                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1505                                         sa = dimm_params[dimm_number].base_address;
1506                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1507                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1508                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1509                                 } else {
1510                                         sa = 0;
1511                                         ea = 0;
1512                                 }
1513                                 if (i == 0)
1514                                         ea += (rank_density >> dbw_cap_adj);
1515                                 break;
1516                         case FSL_DDR_CS2_CS3:
1517                                 /* CS2+CS3 interleaving*/
1518                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1519                                         sa = dimm_params[dimm_number].base_address;
1520                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1521                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1522                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1523                                 } else {
1524                                         sa = 0;
1525                                         ea = 0;
1526                                 }
1527                                 if (i == 2)
1528                                         ea += (rank_density >> dbw_cap_adj);
1529                                 break;
1530                         default:  /* No bank(chip-select) interleaving */
1531                                 break;
1532                         }
1533                 }
1534                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1535                         /*
1536                          * Only the rank on CS0 of each memory controller may
1537                          * be used if memory controller interleaving is used
1538                          * without rank interleaving within each memory
1539                          * controller.  However, the ending address programmed
1540                          * into each CS0 must be the sum of the amount of
1541                          * memory in the two CS0 ranks.
1542                          */
1543                         if (i == 0) {
1544                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1545                         }
1546
1547                 }
1548                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1549                         /*
1550                          * No rank interleaving and no memory controller
1551                          * interleaving.
1552                          */
1553                         sa = dimm_params[dimm_number].base_address;
1554                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1555                         if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1556                                 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1557                                 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1558                         } else {
1559                                 sa = 0;
1560                                 ea = 0;
1561                         }
1562                 }
1563
1564                 sa >>= 24;
1565                 ea >>= 24;
1566
1567                 ddr->cs[i].bnds = (0
1568                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1569                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1570                         );
1571
1572                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1573                 if (cs_en) {
1574                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1575                         set_csn_config_2(i, ddr);
1576                 } else
1577                         printf("CS%d is disabled.\n", i);
1578         }
1579
1580         /*
1581          * In the case we only need to compute the ddr sdram size, we only need
1582          * to set csn registers, so return from here.
1583          */
1584         if (size_only)
1585                 return 0;
1586
1587         set_ddr_eor(ddr, popts);
1588
1589 #if !defined(CONFIG_FSL_DDR1)
1590         set_timing_cfg_0(ddr, popts);
1591 #endif
1592
1593         set_timing_cfg_3(ddr, common_dimm, cas_latency);
1594         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1595         set_timing_cfg_2(ddr, popts, common_dimm,
1596                                 cas_latency, additive_latency);
1597
1598         set_ddr_cdr1(ddr, popts);
1599         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1600         ip_rev = fsl_ddr_get_version();
1601         if (ip_rev > 0x40400)
1602                 unq_mrs_en = 1;
1603
1604         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1605         set_ddr_sdram_mode(ddr, popts, common_dimm,
1606                                 cas_latency, additive_latency, unq_mrs_en);
1607         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1608         set_ddr_sdram_interval(ddr, popts, common_dimm);
1609         set_ddr_data_init(ddr);
1610         set_ddr_sdram_clk_cntl(ddr, popts);
1611         set_ddr_init_addr(ddr);
1612         set_ddr_init_ext_addr(ddr);
1613         set_timing_cfg_4(ddr, popts);
1614         set_timing_cfg_5(ddr, cas_latency);
1615
1616         set_ddr_zq_cntl(ddr, zq_en);
1617         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1618
1619         set_ddr_sr_cntr(ddr, sr_it);
1620
1621         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1622
1623         return check_fsl_memctl_config_regs(ddr);
1624 }