arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_ddr_sdram.h>
  11
  12 #include "ddr.h"
  13
  14 #if defined(CONFIG_FSL_DDR3)
  15 static unsigned int
  16 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
  17                          common_timing_params_t *outpdimm,
  18                          unsigned int number_of_dimms)
  19 {
  20         unsigned int i;
  21         unsigned int tAAmin_ps = 0;
  22         unsigned int tCKmin_X_ps = 0;
  23         unsigned int common_caslat;
  24         unsigned int caslat_actual;
  25         unsigned int retry = 16;
  26         unsigned int tmp;
  27         const unsigned int mclk_ps = get_memory_clk_period_ps();
  28
  29         /* compute the common CAS latency supported between slots */
  30         tmp = dimm_params[0].caslat_X;
  31         for (i = 1; i < number_of_dimms; i++) {
  32                 if (dimm_params[i].n_ranks)
  33                         tmp &= dimm_params[i].caslat_X;
  34         }
  35         common_caslat = tmp;
  36
  37         /* compute the max tAAmin tCKmin between slots */
  38         for (i = 0; i < number_of_dimms; i++) {
  39                 tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
  40                 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
  41         }
  42         /* validate if the memory clk is in the range of dimms */
  43         if (mclk_ps < tCKmin_X_ps) {
  44                 printf("DDR clock (MCLK cycle %u ps) is faster than "
  45                         "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
  46                         mclk_ps, tCKmin_X_ps);
  47         }
  48         /* determine the acutal cas latency */
  49         caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
  50         /* check if the dimms support the CAS latency */
  51         while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
  52                 caslat_actual++;
  53                 retry--;
  54         }
  55         /* once the caculation of caslat_actual is completed
  56          * we must verify that this CAS latency value does not
  57          * exceed tAAmax, which is 20 ns for all DDR3 speed grades
  58          */
  59         if (caslat_actual * mclk_ps > 20000) {
  60                 printf("The choosen cas latency %d is too large\n",
  61                         caslat_actual);
  62         }
  63         outpdimm->lowest_common_SPD_caslat = caslat_actual;
  64
  65         return 0;
  66 }
  67 #endif
  68
  69 /*
  70  * compute_lowest_common_dimm_parameters()
  71  *
  72  * Determine the worst-case DIMM timing parameters from the set of DIMMs
  73  * whose parameters have been computed into the array pointed to
  74  * by dimm_params.
  75  */
  76 unsigned int
  77 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
  78                                       common_timing_params_t *outpdimm,
  79                                       const unsigned int number_of_dimms)
  80 {
  81         unsigned int i, j;
  82
  83         unsigned int tCKmin_X_ps = 0;
  84         unsigned int tCKmax_ps = 0xFFFFFFFF;
  85         unsigned int tCKmax_max_ps = 0;
  86         unsigned int tRCD_ps = 0;
  87         unsigned int tRP_ps = 0;
  88         unsigned int tRAS_ps = 0;
  89         unsigned int tWR_ps = 0;
  90         unsigned int tWTR_ps = 0;
  91         unsigned int tRFC_ps = 0;
  92         unsigned int tRRD_ps = 0;
  93         unsigned int tRC_ps = 0;
  94         unsigned int refresh_rate_ps = 0;
  95         unsigned int tIS_ps = 0;
  96         unsigned int tIH_ps = 0;
  97         unsigned int tDS_ps = 0;
  98         unsigned int tDH_ps = 0;
  99         unsigned int tRTP_ps = 0;
 100         unsigned int tDQSQ_max_ps = 0;
 101         unsigned int tQHS_ps = 0;
 102
 103         unsigned int temp1, temp2;
 104         unsigned int additive_latency = 0;
 105 #if !defined(CONFIG_FSL_DDR3)
 106         const unsigned int mclk_ps = get_memory_clk_period_ps();
 107         unsigned int lowest_good_caslat;
 108         unsigned int not_ok;
 109
 110         debug("using mclk_ps = %u\n", mclk_ps);
 111 #endif
 112
 113         temp1 = 0;
 114         for (i = 0; i < number_of_dimms; i++) {
 115                 /*
 116                  * If there are no ranks on this DIMM,
 117                  * it probably doesn't exist, so skip it.
 118                  */
 119                 if (dimm_params[i].n_ranks == 0) {
 120                         temp1++;
 121                         continue;
 122                 }
 123                 if (dimm_params[i].n_ranks == 4 && i != 0) {
 124                         printf("Found Quad-rank DIMM in wrong bank, ignored."
 125                                 " Software may not run as expected.\n");
 126                         temp1++;
 127                         continue;
 128                 }
 129
 130                 /*
 131                  * check if quad-rank DIMM is plugged if
 132                  * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
 133                  * Only the board with proper design is capable
 134                  */
 135 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 136                 if (dimm_params[i].n_ranks == 4 && \
 137                   CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
 138                         printf("Found Quad-rank DIMM, not able to support.");
 139                         temp1++;
 140                         continue;
 141                 }
 142 #endif
 143                 /*
 144                  * Find minimum tCKmax_ps to find fastest slow speed,
 145                  * i.e., this is the slowest the whole system can go.
 146                  */
 147                 tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
 148
 149                 /* Either find maximum value to determine slowest
 150                  * speed, delay, time, period, etc */
 151                 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
 152                 tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
 153                 tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
 154                 tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
 155                 tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
 156                 tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
 157                 tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
 158                 tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
 159                 tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
 160                 tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
 161                 tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
 162                 tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
 163                 tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
 164                 tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
 165                 tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
 166                 tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
 167                 refresh_rate_ps = max(refresh_rate_ps,
 168                                       dimm_params[i].refresh_rate_ps);
 169
 170                 /*
 171                  * Find maximum tDQSQ_max_ps to find slowest.
 172                  *
 173                  * FIXME: is finding the slowest value the correct
 174                  * strategy for this parameter?
 175                  */
 176                 tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
 177         }
 178
 179         outpdimm->ndimms_present = number_of_dimms - temp1;
 180
 181         if (temp1 == number_of_dimms) {
 182                 debug("no dimms this memory controller\n");
 183                 return 0;
 184         }
 185
 186         outpdimm->tCKmin_X_ps = tCKmin_X_ps;
 187         outpdimm->tCKmax_ps = tCKmax_ps;
 188         outpdimm->tCKmax_max_ps = tCKmax_max_ps;
 189         outpdimm->tRCD_ps = tRCD_ps;
 190         outpdimm->tRP_ps = tRP_ps;
 191         outpdimm->tRAS_ps = tRAS_ps;
 192         outpdimm->tWR_ps = tWR_ps;
 193         outpdimm->tWTR_ps = tWTR_ps;
 194         outpdimm->tRFC_ps = tRFC_ps;
 195         outpdimm->tRRD_ps = tRRD_ps;
 196         outpdimm->tRC_ps = tRC_ps;
 197         outpdimm->refresh_rate_ps = refresh_rate_ps;
 198         outpdimm->tIS_ps = tIS_ps;
 199         outpdimm->tIH_ps = tIH_ps;
 200         outpdimm->tDS_ps = tDS_ps;
 201         outpdimm->tDH_ps = tDH_ps;
 202         outpdimm->tRTP_ps = tRTP_ps;
 203         outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
 204         outpdimm->tQHS_ps = tQHS_ps;
 205
 206         /* Determine common burst length for all DIMMs. */
 207         temp1 = 0xff;
 208         for (i = 0; i < number_of_dimms; i++) {
 209                 if (dimm_params[i].n_ranks) {
 210                         temp1 &= dimm_params[i].burst_lengths_bitmask;
 211                 }
 212         }
 213         outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
 214
 215         /* Determine if all DIMMs registered buffered. */
 216         temp1 = temp2 = 0;
 217         for (i = 0; i < number_of_dimms; i++) {
 218                 if (dimm_params[i].n_ranks) {
 219                         if (dimm_params[i].registered_dimm) {
 220                                 temp1 = 1;
 221 #ifndef CONFIG_SPL_BUILD
 222                                 printf("Detected RDIMM %s\n",
 223                                         dimm_params[i].mpart);
 224 #endif
 225                         } else {
 226                                 temp2 = 1;
 227 #ifndef CONFIG_SPL_BUILD
 228                                 printf("Detected UDIMM %s\n",
 229                                         dimm_params[i].mpart);
 230 #endif
 231                         }
 232                 }
 233         }
 234
 235         outpdimm->all_DIMMs_registered = 0;
 236         outpdimm->all_DIMMs_unbuffered = 0;
 237         if (temp1 && !temp2) {
 238                 outpdimm->all_DIMMs_registered = 1;
 239         } else if (!temp1 && temp2) {
 240                 outpdimm->all_DIMMs_unbuffered = 1;
 241         } else {
 242                 printf("ERROR:  Mix of registered buffered and unbuffered "
 243                                 "DIMMs detected!\n");
 244         }
 245
 246         temp1 = 0;
 247         if (outpdimm->all_DIMMs_registered)
 248                 for (j = 0; j < 16; j++) {
 249                         outpdimm->rcw[j] = dimm_params[0].rcw[j];
 250                         for (i = 1; i < number_of_dimms; i++) {
 251                                 if (!dimm_params[i].n_ranks)
 252                                         continue;
 253                                 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
 254                                         temp1 = 1;
 255                                         break;
 256                                 }
 257                         }
 258                 }
 259
 260         if (temp1 != 0)
 261                 printf("ERROR: Mix different RDIMM detected!\n");
 262
 263 #if defined(CONFIG_FSL_DDR3)
 264         if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
 265                 return 1;
 266 #else
 267         /*
 268          * Compute a CAS latency suitable for all DIMMs
 269          *
 270          * Strategy for SPD-defined latencies: compute only
 271          * CAS latency defined by all DIMMs.
 272          */
 273
 274         /*
 275          * Step 1: find CAS latency common to all DIMMs using bitwise
 276          * operation.
 277          */
 278         temp1 = 0xFF;
 279         for (i = 0; i < number_of_dimms; i++) {
 280                 if (dimm_params[i].n_ranks) {
 281                         temp2 = 0;
 282                         temp2 |= 1 << dimm_params[i].caslat_X;
 283                         temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
 284                         temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
 285                         /*
 286                          * FIXME: If there was no entry for X-2 (X-1) in
 287                          * the SPD, then caslat_X_minus_2
 288                          * (caslat_X_minus_1) contains either 255 or
 289                          * 0xFFFFFFFF because that's what the glorious
 290                          * __ilog2 function returns for an input of 0.
 291                          * On 32-bit PowerPC, left shift counts with bit
 292                          * 26 set (that the value of 255 or 0xFFFFFFFF
 293                          * will have), cause the destination register to
 294                          * be 0.  That is why this works.
 295                          */
 296                         temp1 &= temp2;
 297                 }
 298         }
 299
 300         /*
 301          * Step 2: check each common CAS latency against tCK of each
 302          * DIMM's SPD.
 303          */
 304         lowest_good_caslat = 0;
 305         temp2 = 0;
 306         while (temp1) {
 307                 not_ok = 0;
 308                 temp2 =  __ilog2(temp1);
 309                 debug("checking common caslat = %u\n", temp2);
 310
 311                 /* Check if this CAS latency will work on all DIMMs at tCK. */
 312                 for (i = 0; i < number_of_dimms; i++) {
 313                         if (!dimm_params[i].n_ranks) {
 314                                 continue;
 315                         }
 316                         if (dimm_params[i].caslat_X == temp2) {
 317                                 if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
 318                                         debug("CL = %u ok on DIMM %u at tCK=%u"
 319                                             " ps with its tCKmin_X_ps of %u\n",
 320                                                temp2, i, mclk_ps,
 321                                                dimm_params[i].tCKmin_X_ps);
 322                                         continue;
 323                                 } else {
 324                                         not_ok++;
 325                                 }
 326                         }
 327
 328                         if (dimm_params[i].caslat_X_minus_1 == temp2) {
 329                                 unsigned int tCKmin_X_minus_1_ps
 330                                         = dimm_params[i].tCKmin_X_minus_1_ps;
 331                                 if (mclk_ps >= tCKmin_X_minus_1_ps) {
 332                                         debug("CL = %u ok on DIMM %u at "
 333                                                 "tCK=%u ps with its "
 334                                                 "tCKmin_X_minus_1_ps of %u\n",
 335                                                temp2, i, mclk_ps,
 336                                                tCKmin_X_minus_1_ps);
 337                                         continue;
 338                                 } else {
 339                                         not_ok++;
 340                                 }
 341                         }
 342
 343                         if (dimm_params[i].caslat_X_minus_2 == temp2) {
 344                                 unsigned int tCKmin_X_minus_2_ps
 345                                         = dimm_params[i].tCKmin_X_minus_2_ps;
 346                                 if (mclk_ps >= tCKmin_X_minus_2_ps) {
 347                                         debug("CL = %u ok on DIMM %u at "
 348                                                 "tCK=%u ps with its "
 349                                                 "tCKmin_X_minus_2_ps of %u\n",
 350                                                temp2, i, mclk_ps,
 351                                                tCKmin_X_minus_2_ps);
 352                                         continue;
 353                                 } else {
 354                                         not_ok++;
 355                                 }
 356                         }
 357                 }
 358
 359                 if (!not_ok) {
 360                         lowest_good_caslat = temp2;
 361                 }
 362
 363                 temp1 &= ~(1 << temp2);
 364         }
 365
 366         debug("lowest common SPD-defined CAS latency = %u\n",
 367                lowest_good_caslat);
 368         outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
 369
 370
 371         /*
 372          * Compute a common 'de-rated' CAS latency.
 373          *
 374          * The strategy here is to find the *highest* dereated cas latency
 375          * with the assumption that all of the DIMMs will support a dereated
 376          * CAS latency higher than or equal to their lowest dereated value.
 377          */
 378         temp1 = 0;
 379         for (i = 0; i < number_of_dimms; i++) {
 380                 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
 381         }
 382         outpdimm->highest_common_derated_caslat = temp1;
 383         debug("highest common dereated CAS latency = %u\n", temp1);
 384 #endif /* #if defined(CONFIG_FSL_DDR3) */
 385
 386         /* Determine if all DIMMs ECC capable. */
 387         temp1 = 1;
 388         for (i = 0; i < number_of_dimms; i++) {
 389                 if (dimm_params[i].n_ranks &&
 390                         !(dimm_params[i].edc_config & EDC_ECC)) {
 391                         temp1 = 0;
 392                         break;
 393                 }
 394         }
 395         if (temp1) {
 396                 debug("all DIMMs ECC capable\n");
 397         } else {
 398                 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
 399         }
 400         outpdimm->all_DIMMs_ECC_capable = temp1;
 401
 402 #ifndef CONFIG_FSL_DDR3
 403         /* FIXME: move to somewhere else to validate. */
 404         if (mclk_ps > tCKmax_max_ps) {
 405                 printf("Warning: some of the installed DIMMs "
 406                                 "can not operate this slowly.\n");
 407                 return 1;
 408         }
 409 #endif
 410         /*
 411          * Compute additive latency.
 412          *
 413          * For DDR1, additive latency should be 0.
 414          *
 415          * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
 416          *      which comes from Trcd, and also note that:
 417          *          add_lat + caslat must be >= 4
 418          *
 419          * For DDR3, we use the AL=0
 420          *
 421          * When to use additive latency for DDR2:
 422          *
 423          * I. Because you are using CL=3 and need to do ODT on writes and
 424          *    want functionality.
 425          *    1. Are you going to use ODT? (Does your board not have
 426          *      additional termination circuitry for DQ, DQS, DQS_,
 427          *      DM, RDQS, RDQS_ for x4/x8 configs?)
 428          *    2. If so, is your lowest supported CL going to be 3?
 429          *    3. If so, then you must set AL=1 because
 430          *
 431          *       WL >= 3 for ODT on writes
 432          *       RL = AL + CL
 433          *       WL = RL - 1
 434          *       ->
 435          *       WL = AL + CL - 1
 436          *       AL + CL - 1 >= 3
 437          *       AL + CL >= 4
 438          *  QED
 439          *
 440          *  RL >= 3 for ODT on reads
 441          *  RL = AL + CL
 442          *
 443          *  Since CL aren't usually less than 2, AL=0 is a minimum,
 444          *  so the WL-derived AL should be the  -- FIXME?
 445          *
 446          * II. Because you are using auto-precharge globally and want to
 447          *     use additive latency (posted CAS) to get more bandwidth.
 448          *     1. Are you going to use auto-precharge mode globally?
 449          *
 450          *        Use addtivie latency and compute AL to be 1 cycle less than
 451          *        tRCD, i.e. the READ or WRITE command is in the cycle
 452          *        immediately following the ACTIVATE command..
 453          *
 454          * III. Because you feel like it or want to do some sort of
 455          *      degraded-performance experiment.
 456          *     1.  Do you just want to use additive latency because you feel
 457          *         like it?
 458          *
 459          * Validation:  AL is less than tRCD, and within the other
 460          * read-to-precharge constraints.
 461          */
 462
 463         additive_latency = 0;
 464
 465 #if defined(CONFIG_FSL_DDR2)
 466         if (lowest_good_caslat < 4) {
 467                 additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
 468                         ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
 469                 if (mclk_to_picos(additive_latency) > tRCD_ps) {
 470                         additive_latency = picos_to_mclk(tRCD_ps);
 471                         debug("setting additive_latency to %u because it was "
 472                                 " greater than tRCD_ps\n", additive_latency);
 473                 }
 474         }
 475
 476 #elif defined(CONFIG_FSL_DDR3)
 477         /*
 478          * The system will not use the global auto-precharge mode.
 479          * However, it uses the page mode, so we set AL=0
 480          */
 481         additive_latency = 0;
 482 #endif
 483
 484         /*
 485          * Validate additive latency
 486          * FIXME: move to somewhere else to validate
 487          *
 488          * AL <= tRCD(min)
 489          */
 490         if (mclk_to_picos(additive_latency) > tRCD_ps) {
 491                 printf("Error: invalid additive latency exceeds tRCD(min).\n");
 492                 return 1;
 493         }
 494
 495         /*
 496          * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
 497          * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
 498          * ADD_LAT (the register) must be set to a value less
 499          * than ACTTORW if WL = 1, then AL must be set to 1
 500          * RD_TO_PRE (the register) must be set to a minimum
 501          * tRTP + AL if AL is nonzero
 502          */
 503
 504         /*
 505          * Additive latency will be applied only if the memctl option to
 506          * use it.
 507          */
 508         outpdimm->additive_latency = additive_latency;
 509
 510         debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
 511         debug("tRCD_ps   = %u\n", outpdimm->tRCD_ps);
 512         debug("tRP_ps    = %u\n", outpdimm->tRP_ps);
 513         debug("tRAS_ps   = %u\n", outpdimm->tRAS_ps);
 514         debug("tWR_ps    = %u\n", outpdimm->tWR_ps);
 515         debug("tWTR_ps   = %u\n", outpdimm->tWTR_ps);
 516         debug("tRFC_ps   = %u\n", outpdimm->tRFC_ps);
 517         debug("tRRD_ps   = %u\n", outpdimm->tRRD_ps);
 518         debug("tRC_ps    = %u\n", outpdimm->tRC_ps);
 519
 520         return 0;
 521 }