arch/powerpc/cpu/mpc8xxx/ddr/util.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_law.h>
  11 #include <div64.h>
  12
  13 #include "ddr.h"
  14
  15 /* To avoid 64-bit full-divides, we factor this here */
  16 #define ULL_2E12 2000000000000ULL
  17 #define UL_5POW12 244140625UL
  18 #define UL_2POW13 (1UL << 13)
  19
  20 #define ULL_8FS 0xFFFFFFFFULL
  21
  22 /*
  23  * Round up mclk_ps to nearest 1 ps in memory controller code
  24  * if the error is 0.5ps or more.
  25  *
  26  * If an imprecise data rate is too high due to rounding error
  27  * propagation, compute a suitably rounded mclk_ps to compute
  28  * a working memory controller configuration.
  29  */
  30 unsigned int get_memory_clk_period_ps(void)
  31 {
  32         unsigned int data_rate = get_ddr_freq(0);
  33         unsigned int result;
  34
  35         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  36         unsigned long long rem, mclk_ps = ULL_2E12;
  37
  38         /* Now perform the big divide, the result fits in 32-bits */
  39         rem = do_div(mclk_ps, data_rate);
  40         result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
  41
  42         return result;
  43 }
  44
  45 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  46 unsigned int picos_to_mclk(unsigned int picos)
  47 {
  48         unsigned long long clks, clks_rem;
  49         unsigned long data_rate = get_ddr_freq(0);
  50
  51         /* Short circuit for zero picos */
  52         if (!picos)
  53                 return 0;
  54
  55         /* First multiply the time by the data rate (32x32 => 64) */
  56         clks = picos * (unsigned long long)data_rate;
  57         /*
  58          * Now divide by 5^12 and track the 32-bit remainder, then divide
  59          * by 2*(2^12) using shifts (and updating the remainder).
  60          */
  61         clks_rem = do_div(clks, UL_5POW12);
  62         clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
  63         clks >>= 13;
  64
  65         /* If we had a remainder greater than the 1ps error, then round up */
  66         if (clks_rem > data_rate)
  67                 clks++;
  68
  69         /* Clamp to the maximum representable value */
  70         if (clks > ULL_8FS)
  71                 clks = ULL_8FS;
  72         return (unsigned int) clks;
  73 }
  74
  75 unsigned int mclk_to_picos(unsigned int mclk)
  76 {
  77         return get_memory_clk_period_ps() * mclk;
  78 }
  79
  80 void
  81 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
  82                            unsigned int law_memctl,
  83                            unsigned int ctrl_num)
  84 {
  85         unsigned long long base = memctl_common_params->base_address;
  86         unsigned long long size = memctl_common_params->total_mem;
  87
  88         /*
  89          * If no DIMMs on this controller, do not proceed any further.
  90          */
  91         if (!memctl_common_params->ndimms_present) {
  92                 return;
  93         }
  94
  95 #if !defined(CONFIG_PHYS_64BIT)
  96         if (base >= CONFIG_MAX_MEM_MAPPED)
  97                 return;
  98         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
  99                 size = CONFIG_MAX_MEM_MAPPED - base;
 100 #endif
 101         if (set_ddr_laws(base, size, law_memctl) < 0) {
 102                 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
 103                         law_memctl);
 104                 return ;
 105         }
 106         debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
 107                 base, size, law_memctl);
 108 }
 109
 110 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 111 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 112                          unsigned int memctl_interleaved,
 113                          unsigned int ctrl_num);
 114
 115 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 116 {
 117 #ifdef CONFIG_E6500
 118         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 119         *mcintl3r = 0x80000000 | (granule_size & 0x1f);
 120         debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
 121 #endif
 122 }
 123
 124 u32 fsl_ddr_get_intl3r(void)
 125 {
 126         u32 val = 0;
 127 #ifdef CONFIG_E6500
 128         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 129         val = *mcintl3r;
 130 #endif
 131         return val;
 132 }
 133
 134 void board_add_ram_info(int use_default)
 135 {
 136 #if defined(CONFIG_MPC83xx)
 137         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 138         ccsr_ddr_t *ddr = (void *)&immap->ddr;
 139 #elif defined(CONFIG_MPC85xx)
 140         ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 141 #elif defined(CONFIG_MPC86xx)
 142         ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 143 #endif
 144 #if     defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
 145         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 146 #endif
 147 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 148         uint32_t cs0_config = in_be32(&ddr->cs0_config);
 149 #endif
 150         uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 151         int cas_lat;
 152
 153 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
 154         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 155                 ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
 156                 sdram_cfg = in_be32(&ddr->sdram_cfg);
 157         }
 158 #endif
 159 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
 160         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 161                 ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
 162                 sdram_cfg = in_be32(&ddr->sdram_cfg);
 163         }
 164 #endif
 165         puts(" (DDR");
 166         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 167                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 168         case SDRAM_TYPE_DDR1:
 169                 puts("1");
 170                 break;
 171         case SDRAM_TYPE_DDR2:
 172                 puts("2");
 173                 break;
 174         case SDRAM_TYPE_DDR3:
 175                 puts("3");
 176                 break;
 177         default:
 178                 puts("?");
 179                 break;
 180         }
 181
 182         if (sdram_cfg & SDRAM_CFG_32_BE)
 183                 puts(", 32-bit");
 184         else if (sdram_cfg & SDRAM_CFG_16_BE)
 185                 puts(", 16-bit");
 186         else
 187                 puts(", 64-bit");
 188
 189         /* Calculate CAS latency based on timing cfg values */
 190         cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
 191         if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
 192                 cas_lat += (8 << 1);
 193         printf(", CL=%d", cas_lat >> 1);
 194         if (cas_lat & 0x1)
 195                 puts(".5");
 196
 197         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 198                 puts(", ECC on)");
 199         else
 200                 puts(", ECC off)");
 201
 202 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
 203 #ifdef CONFIG_E6500
 204         if (*mcintl3r & 0x80000000) {
 205                 puts("\n");
 206                 puts("       DDR Controller Interleaving Mode: ");
 207                 switch (*mcintl3r & 0x1f) {
 208                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 209                         puts("3-way 1KB");
 210                         break;
 211                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 212                         puts("3-way 4KB");
 213                         break;
 214                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 215                         puts("3-way 8KB");
 216                         break;
 217                 default:
 218                         puts("3-way UNKNOWN");
 219                         break;
 220                 }
 221         }
 222 #endif
 223 #endif
 224 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 225         if (cs0_config & 0x20000000) {
 226                 puts("\n");
 227                 puts("       DDR Controller Interleaving Mode: ");
 228
 229                 switch ((cs0_config >> 24) & 0xf) {
 230                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 231                         puts("cache line");
 232                         break;
 233                 case FSL_DDR_PAGE_INTERLEAVING:
 234                         puts("page");
 235                         break;
 236                 case FSL_DDR_BANK_INTERLEAVING:
 237                         puts("bank");
 238                         break;
 239                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 240                         puts("super-bank");
 241                         break;
 242                 default:
 243                         puts("invalid");
 244                         break;
 245                 }
 246         }
 247 #endif
 248
 249         if ((sdram_cfg >> 8) & 0x7f) {
 250                 puts("\n");
 251                 puts("       DDR Chip-Select Interleaving Mode: ");
 252                 switch(sdram_cfg >> 8 & 0x7f) {
 253                 case FSL_DDR_CS0_CS1_CS2_CS3:
 254                         puts("CS0+CS1+CS2+CS3");
 255                         break;
 256                 case FSL_DDR_CS0_CS1:
 257                         puts("CS0+CS1");
 258                         break;
 259                 case FSL_DDR_CS2_CS3:
 260                         puts("CS2+CS3");
 261                         break;
 262                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 263                         puts("CS0+CS1 and CS2+CS3");
 264                         break;
 265                 default:
 266                         puts("invalid");
 267                         break;
 268                 }
 269         }
 270 }