arch/x86/dts/crownbay.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "serial.dtsi"
  13
  14 / {
  15         model = "Intel Crown Bay";
  16         compatible = "intel,crownbay", "intel,queensbay";
  17
  18         aliases {
  19                 spi0 = "/spi";
  20         };
  21
  22         config {
  23                 silent_console = <0>;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "cpu-x86";
  33                         reg = <0>;
  34                         intel,apic-id = <0>;
  35                 };
  36
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "cpu-x86";
  40                         reg = <1>;
  41                         intel,apic-id = <1>;
  42                 };
  43
  44         };
  45
  46         gpioa {
  47                 compatible = "intel,ich6-gpio";
  48                 u-boot,dm-pre-reloc;
  49                 reg = <0 0x20>;
  50                 bank-name = "A";
  51         };
  52
  53         gpiob {
  54                 compatible = "intel,ich6-gpio";
  55                 u-boot,dm-pre-reloc;
  56                 reg = <0x20 0x20>;
  57                 bank-name = "B";
  58         };
  59
  60         chosen {
  61                 /*
  62                  * By default the legacy superio serial port is used as the
  63                  * U-Boot serial console. If we want to use UART from Topcliff
  64                  * PCH as the console, change this property to &pciuart#.
  65                  *
  66                  * For example, stdout-path = &pciuart0 will use the first
  67                  * UART on Topcliff PCH.
  68                  */
  69                 stdout-path = "/serial";
  70         };
  71
  72         spi {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75                 compatible = "intel,ich-spi";
  76                 spi-flash@0 {
  77                         reg = <0>;
  78                         compatible = "sst,25vf016b", "spi-flash";
  79                         memory-map = <0xffe00000 0x00200000>;
  80                 };
  81         };
  82
  83         microcode {
  84                 update@0 {
  85 #include "microcode/m0220661105_cv.dtsi"
  86                 };
  87         };
  88
  89         pci {
  90                 #address-cells = <3>;
  91                 #size-cells = <2>;
  92                 compatible = "intel,pci";
  93                 device_type = "pci";
  94
  95                 pcie@17,0 {
  96                         #address-cells = <3>;
  97                         #size-cells = <2>;
  98                         compatible = "intel,pci";
  99                         device_type = "pci";
 100
 101                         topcliff@0,0 {
 102                                 #address-cells = <3>;
 103                                 #size-cells = <2>;
 104                                 compatible = "intel,pci";
 105                                 device_type = "pci";
 106
 107                                 pciuart0: uart@a,1 {
 108                                         compatible = "pci8086,8811.00",
 109                                                         "pci8086,8811",
 110                                                         "pciclass,070002",
 111                                                         "pciclass,0700",
 112                                                         "x86-uart";
 113                                         reg = <0x00025100 0x0 0x0 0x0 0x0
 114                                                0x01025110 0x0 0x0 0x0 0x0>;
 115                                         reg-shift = <0>;
 116                                         clock-frequency = <1843200>;
 117                                         current-speed = <115200>;
 118                                 };
 119
 120                                 pciuart1: uart@a,2 {
 121                                         compatible = "pci8086,8812.00",
 122                                                         "pci8086,8812",
 123                                                         "pciclass,070002",
 124                                                         "pciclass,0700",
 125                                                         "x86-uart";
 126                                         reg = <0x00025200 0x0 0x0 0x0 0x0
 127                                                0x01025210 0x0 0x0 0x0 0x0>;
 128                                         reg-shift = <0>;
 129                                         clock-frequency = <1843200>;
 130                                         current-speed = <115200>;
 131                                 };
 132
 133                                 pciuart2: uart@a,3 {
 134                                         compatible = "pci8086,8813.00",
 135                                                         "pci8086,8813",
 136                                                         "pciclass,070002",
 137                                                         "pciclass,0700",
 138                                                         "x86-uart";
 139                                         reg = <0x00025300 0x0 0x0 0x0 0x0
 140                                                0x01025310 0x0 0x0 0x0 0x0>;
 141                                         reg-shift = <0>;
 142                                         clock-frequency = <1843200>;
 143                                         current-speed = <115200>;
 144                                 };
 145
 146                                 pciuart3: uart@a,4 {
 147                                         compatible = "pci8086,8814.00",
 148                                                         "pci8086,8814",
 149                                                         "pciclass,070002",
 150                                                         "pciclass,0700",
 151                                                         "x86-uart";
 152                                         reg = <0x00025400 0x0 0x0 0x0 0x0
 153                                                0x01025410 0x0 0x0 0x0 0x0>;
 154                                         reg-shift = <0>;
 155                                         clock-frequency = <1843200>;
 156                                         current-speed = <115200>;
 157                                 };
 158                         };
 159                 };
 160
 161                 irq-router@1f,0 {
 162                         reg = <0x0000f800 0 0 0 0>;
 163                         compatible = "intel,irq-router";
 164                         intel,pirq-config = "pci";
 165                         intel,pirq-link = <0x60 8>;
 166                         intel,pirq-mask = <0xdee0>;
 167                         intel,pirq-routing = <
 168                                 /* TunnelCreek PCI devices */
 169                                 PCI_BDF(0, 2, 0) INTA PIRQE
 170                                 PCI_BDF(0, 3, 0) INTA PIRQF
 171                                 PCI_BDF(0, 23, 0) INTA PIRQE
 172                                 PCI_BDF(0, 24, 0) INTA PIRQF
 173                                 PCI_BDF(0, 25, 0) INTA PIRQG
 174                                 PCI_BDF(0, 26, 0) INTA PIRQH
 175                                 PCI_BDF(0, 27, 0) INTA PIRQG
 176                                 /*
 177                                  * Topcliff PCI devices
 178                                  *
 179                                  * Note on the Crown Bay board, Topcliff chipset
 180                                  * is connected to TunnelCreek PCIe port 0, so
 181                                  * its bus number is 1 for its PCIe port and 2
 182                                  * for its PCI devices per U-Boot currnet PCI
 183                                  * bus enumeration algorithm.
 184                                  */
 185                                 PCI_BDF(1, 0, 0) INTA PIRQA
 186                                 PCI_BDF(2, 0, 1) INTA PIRQA
 187                                 PCI_BDF(2, 0, 2) INTA PIRQA
 188                                 PCI_BDF(2, 2, 0) INTB PIRQB
 189                                 PCI_BDF(2, 2, 1) INTB PIRQB
 190                                 PCI_BDF(2, 2, 2) INTB PIRQB
 191                                 PCI_BDF(2, 2, 3) INTB PIRQB
 192                                 PCI_BDF(2, 2, 4) INTB PIRQB
 193                                 PCI_BDF(2, 4, 0) INTC PIRQC
 194                                 PCI_BDF(2, 4, 1) INTC PIRQC
 195                                 PCI_BDF(2, 6, 0) INTD PIRQD
 196                                 PCI_BDF(2, 8, 0) INTA PIRQA
 197                                 PCI_BDF(2, 8, 1) INTA PIRQA
 198                                 PCI_BDF(2, 8, 2) INTA PIRQA
 199                                 PCI_BDF(2, 8, 3) INTA PIRQA
 200                                 PCI_BDF(2, 10, 0) INTB PIRQB
 201                                 PCI_BDF(2, 10, 1) INTB PIRQB
 202                                 PCI_BDF(2, 10, 2) INTB PIRQB
 203                                 PCI_BDF(2, 10, 3) INTB PIRQB
 204                                 PCI_BDF(2, 10, 4) INTB PIRQB
 205                                 PCI_BDF(2, 12, 0) INTC PIRQC
 206                                 PCI_BDF(2, 12, 1) INTC PIRQC
 207                                 PCI_BDF(2, 12, 2) INTC PIRQC
 208                                 PCI_BDF(2, 12, 3) INTC PIRQC
 209                                 PCI_BDF(2, 12, 4) INTC PIRQC
 210                         >;
 211                 };
 212         };
 213
 214 };