board/Marvell/rd6281a/rd6281a.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14 #include <asm/arch/mpp.h>
  15 #include "rd6281a.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int board_early_init_f(void)
  20 {
  21         /*
  22          * default gpio configuration
  23          * There are maximum 64 gpios controlled through 2 sets of registers
  24          * the  below configuration configures mainly initial LED status
  25          */
  26         mvebu_config_gpio(RD6281A_OE_VAL_LOW,
  27                           RD6281A_OE_VAL_HIGH,
  28                           RD6281A_OE_LOW, RD6281A_OE_HIGH);
  29
  30         /* Multi-Purpose Pins Functionality configuration */
  31         static const u32 kwmpp_config[] = {
  32                 MPP0_NF_IO2,
  33                 MPP1_NF_IO3,
  34                 MPP2_NF_IO4,
  35                 MPP3_NF_IO5,
  36                 MPP4_NF_IO6,
  37                 MPP5_NF_IO7,
  38                 MPP6_SYSRST_OUTn,
  39                 MPP7_GPO,
  40                 MPP8_TW_SDA,
  41                 MPP9_TW_SCK,
  42                 MPP10_UART0_TXD,
  43                 MPP11_UART0_RXD,
  44                 MPP12_SD_CLK,
  45                 MPP13_SD_CMD,
  46                 MPP14_SD_D0,
  47                 MPP15_SD_D1,
  48                 MPP16_SD_D2,
  49                 MPP17_SD_D3,
  50                 MPP18_NF_IO0,
  51                 MPP19_NF_IO1,
  52                 MPP20_GE1_0,
  53                 MPP21_GE1_1,
  54                 MPP22_GE1_2,
  55                 MPP23_GE1_3,
  56                 MPP24_GE1_4,
  57                 MPP25_GE1_5,
  58                 MPP26_GE1_6,
  59                 MPP27_GE1_7,
  60                 MPP28_GPIO,
  61                 MPP29_GPIO,
  62                 MPP30_GE1_10,
  63                 MPP31_GE1_11,
  64                 MPP32_GE1_12,
  65                 MPP33_GE1_13,
  66                 MPP34_GE1_14,
  67                 MPP35_GPIO,
  68                 MPP36_AUDIO_SPDIFI,
  69                 MPP37_AUDIO_SPDIFO,
  70                 MPP38_GPIO,
  71                 MPP39_TDM_SPI_CS0,
  72                 MPP40_TDM_SPI_SCK,
  73                 MPP41_TDM_SPI_MISO,
  74                 MPP42_TDM_SPI_MOSI,
  75                 MPP43_TDM_CODEC_INTn,
  76                 MPP44_GPIO,
  77                 MPP45_TDM_PCLK,
  78                 MPP46_TDM_FS,
  79                 MPP47_TDM_DRX,
  80                 MPP48_TDM_DTX,
  81                 MPP49_GPIO,
  82                 0
  83         };
  84         kirkwood_mpp_conf(kwmpp_config, NULL);
  85         return 0;
  86 }
  87
  88 int board_init(void)
  89 {
  90         /*
  91          * arch number of board
  92          */
  93         gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
  94
  95         /* adress of boot parameters */
  96         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  97
  98         return 0;
  99 }
 100
 101 void mv_phy_88e1116_init(char *name)
 102 {
 103         u16 reg;
 104         u16 devadr;
 105
 106         if (miiphy_set_current_dev(name))
 107                 return;
 108
 109         /* command to read PHY dev address */
 110         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 111                 printf("Err..%s could not read PHY dev address\n",
 112                         __FUNCTION__);
 113                 return;
 114         }
 115
 116         /*
 117          * Enable RGMII delay on Tx and Rx for CPU port
 118          * Ref: sec 4.7.2 of chip datasheet
 119          */
 120         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 121         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 122         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 123         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 124         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 125
 126         /* reset the phy */
 127         if (miiphy_read (name, devadr, MII_BMCR, &reg) != 0) {
 128                 printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
 129                 return;
 130         }
 131         if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
 132                 printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
 133                 return;
 134         }
 135
 136         printf("88E1116 Initialized on %s\n", name);
 137 }
 138
 139 /* Configure and enable Switch and PHY */
 140 void reset_phy(void)
 141 {
 142         /* configure and initialize switch */
 143         struct mv88e61xx_config swcfg = {
 144                 .name = "egiga0",
 145                 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
 146                 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
 147                 .led_init = MV88E61XX_LED_INIT_EN,
 148                 .portstate = MV88E61XX_PORTSTT_FORWARDING,
 149                 .cpuport = (1 << 5),
 150                 .ports_enabled = 0x3f,
 151         };
 152
 153         mv88e61xx_switch_initialize(&swcfg);
 154
 155         /* configure and initialize PHY */
 156         mv_phy_88e1116_init("egiga1");
 157 }