board/amcc/ebony/ebony.c

   1 /*
   2  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/processor.h>
   9 #include <spd_sdram.h>
  10
  11 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  12 #define FLASH_ONBD_N            2       /* 00000010 */
  13 #define FLASH_SRAM_SEL          1       /* 00000001 */
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 long int fixed_sdram(void);
  18
  19 int board_early_init_f(void)
  20 {
  21         uint reg;
  22         unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
  23         unsigned char status;
  24
  25         /*--------------------------------------------------------------------
  26          * Setup the external bus controller/chip selects
  27          *-------------------------------------------------------------------*/
  28         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  29         reg = mfdcr(EBC0_CFGDATA);
  30         mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
  31
  32         mtebc(PB1AP, 0x02815480);       /* NVRAM/RTC */
  33         mtebc(PB1CR, 0x48018000);       /* BA=0x480 1MB R/W 8-bit */
  34         mtebc(PB7AP, 0x01015280);       /* FPGA registers */
  35         mtebc(PB7CR, 0x48318000);       /* BA=0x483 1MB R/W 8-bit */
  36
  37         /* read FPGA_REG0  and set the bus controller */
  38         status = *fpga_base;
  39         if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
  40                 mtebc(PB0AP, 0x9b015480);       /* FLASH/SRAM */
  41                 mtebc(PB0CR, 0xfff18000);       /* BAS=0xfff 1MB R/W 8-bit */
  42                 mtebc(PB2AP, 0x9b015480);       /* 4MB FLASH */
  43                 mtebc(PB2CR, 0xff858000);       /* BAS=0xff8 4MB R/W 8-bit */
  44         } else {
  45                 mtebc(PB0AP, 0x9b015480);       /* 4MB FLASH */
  46                 mtebc(PB0CR, 0xffc58000);       /* BAS=0xffc 4MB R/W 8-bit */
  47
  48                 /* set CS2 if FLASH_ONBD_N == 0 */
  49                 if (!(status & FLASH_ONBD_N)) {
  50                         mtebc(PB2AP, 0x9b015480);       /* FLASH/SRAM */
  51                         mtebc(PB2CR, 0xff818000);       /* BAS=0xff8 4MB R/W 8-bit */
  52                 }
  53         }
  54
  55         /*--------------------------------------------------------------------
  56          * Setup the interrupt controller polarities, triggers, etc.
  57          *-------------------------------------------------------------------*/
  58         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  59         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  60         mtdcr(UIC0CR, 0x00000009);      /* SMI & UIC1 crit are critical */
  61         mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  62         mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  63         mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  64         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  65
  66         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  67         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  68         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  69         mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
  70         mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
  71         mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
  72         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  73
  74         return 0;
  75 }
  76
  77 int checkboard(void)
  78 {
  79         char buf[64];
  80         int i = getenv_f("serial#", buf, sizeof(buf));
  81
  82         printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
  83         if (i > 0) {
  84                 puts(", serial# ");
  85                 puts(buf);
  86         }
  87         putc('\n');
  88
  89         return (0);
  90 }
  91
  92 phys_size_t initdram(int board_type)
  93 {
  94         long dram_size = 0;
  95
  96 #if defined(CONFIG_SPD_EEPROM)
  97         dram_size = spd_sdram();
  98 #else
  99         dram_size = fixed_sdram();
 100 #endif
 101         return dram_size;
 102 }
 103
 104 #if !defined(CONFIG_SPD_EEPROM)
 105 /*************************************************************************
 106  *  fixed sdram init -- doesn't use serial presence detect.
 107  *
 108  *  Assumes:    128 MB, non-ECC, non-registered
 109  *              PLB @ 133 MHz
 110  *
 111  ************************************************************************/
 112 long int fixed_sdram(void)
 113 {
 114         uint reg;
 115
 116         /*--------------------------------------------------------------------
 117          * Setup some default
 118          *------------------------------------------------------------------*/
 119         mtsdram(SDRAM0_UABBA, 0x00000000);      /* ubba=0 (default)             */
 120         mtsdram(SDRAM0_SLIO, 0x00000000);       /* rdre=0 wrre=0 rarw=0         */
 121         mtsdram(SDRAM0_DEVOPT, 0x00000000);     /* dll=0 ds=0 (normal)          */
 122         mtsdram(SDRAM0_WDDCTR, 0x00000000);     /* wrcp=0 dcd=0                 */
 123         mtsdram(SDRAM0_CLKTR, 0x40000000);      /* clkp=1 (90 deg wr) dcdt=0    */
 124
 125         /*--------------------------------------------------------------------
 126          * Setup for board-specific specific mem
 127          *------------------------------------------------------------------*/
 128         /*
 129          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 130          */
 131         mtsdram(SDRAM0_B0CR, 0x000a4001);       /* SDBA=0x000 128MB, Mode 3, enabled */
 132         mtsdram(SDRAM0_TR0, 0x410a4012);        /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 133         /* RA=10 RD=3                       */
 134         mtsdram(SDRAM0_TR1, 0x8080082f);        /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 135         mtsdram(SDRAM0_RTR, 0x08200000);        /* Rate 15.625 ns @ 133 MHz PLB     */
 136         mtsdram(SDRAM0_CFG1, 0x00000000);       /* Self-refresh exit, disable PM    */
 137         udelay(400);            /* Delay 200 usecs (min)            */
 138
 139         /*--------------------------------------------------------------------
 140          * Enable the controller, then wait for DCEN to complete
 141          *------------------------------------------------------------------*/
 142         mtsdram(SDRAM0_CFG0, 0x86000000);       /* DCEN=1, PMUD=1, 64-bit           */
 143         for (;;) {
 144                 mfsdram(SDRAM0_MCSTS, reg);
 145                 if (reg & 0x80000000)
 146                         break;
 147         }
 148
 149         return (128 * 1024 * 1024);     /* 128 MB                           */
 150 }
 151 #endif                          /* !defined(CONFIG_SPD_EEPROM) */