board/atmel/at91sam9rlek/at91sam9rlek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9rl.h>
  27 #include <asm/arch/at91sam9rl_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_common.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/at91_rstc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34 #include <lcd.h>
  35 #include <atmel_lcdc.h>
  36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  37 #include <net.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* ------------------------------------------------------------------------- */
  43 /*
  44  * Miscelaneous platform dependent initialisations
  45  */
  46
  47 #ifdef CONFIG_CMD_NAND
  48 static void at91sam9rlek_nand_hw_init(void)
  49 {
  50         unsigned long csa;
  51
  52         /* Enable CS3 */
  53         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  54         at91_sys_write(AT91_MATRIX_EBICSA,
  55                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  56
  57         /* Configure SMC CS3 for NAND/SmartMedia */
  58         at91_sys_write(AT91_SMC_SETUP(3),
  59                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  60                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  61         at91_sys_write(AT91_SMC_PULSE(3),
  62                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  63                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  64         at91_sys_write(AT91_SMC_CYCLE(3),
  65                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  66         at91_sys_write(AT91_SMC_MODE(3),
  67                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  68                        AT91_SMC_EXNWMODE_DISABLE |
  69 #ifdef CONFIG_SYS_NAND_DBW_16
  70                        AT91_SMC_DBW_16 |
  71 #else /* CONFIG_SYS_NAND_DBW_8 */
  72                        AT91_SMC_DBW_8 |
  73 #endif
  74                        AT91_SMC_TDF_(2));
  75
  76         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
  77
  78         /* Configure RDY/BSY */
  79         at91_set_gpio_input(AT91_PIN_PD17, 1);
  80
  81         /* Enable NandFlash */
  82         at91_set_gpio_output(AT91_PIN_PB6, 1);
  83
  84         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
  85         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_HAS_DATAFLASH
  90 static void at91sam9rlek_spi_hw_init(void)
  91 {
  92         at91_set_A_periph(AT91_PIN_PA28, 0);    /* SPI0_NPCS0 */
  93
  94         at91_set_A_periph(AT91_PIN_PA25, 0);    /* SPI0_MISO */
  95         at91_set_A_periph(AT91_PIN_PA26, 0);    /* SPI0_MOSI */
  96         at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPI0_SPCK */
  97
  98         /* Enable clock */
  99         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
 100 }
 101 #endif
 102
 103 #ifdef CONFIG_LCD
 104 vidinfo_t panel_info = {
 105         vl_col:         240,
 106         vl_row:         320,
 107         vl_clk:         4965000,
 108         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 109                         ATMEL_LCDC_INVFRAME_INVERTED,
 110         vl_bpix:        3,
 111         vl_tft:         1,
 112         vl_hsync_len:   5,
 113         vl_left_margin: 1,
 114         vl_right_margin:33,
 115         vl_vsync_len:   1,
 116         vl_upper_margin:1,
 117         vl_lower_margin:0,
 118         mmio:           AT91SAM9RL_LCDC_BASE,
 119 };
 120
 121 void lcd_enable(void)
 122 {
 123         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
 124 }
 125
 126 void lcd_disable(void)
 127 {
 128         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 129 }
 130 static void at91sam9rlek_lcd_hw_init(void)
 131 {
 132         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 133         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 134         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 135         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 136         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 137         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 138         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 139         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 140         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 141         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 142         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 143         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 144         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 145         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 146         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 147         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 148         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 149         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 150         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 151         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 152         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 153
 154         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
 155
 156         gd->fb_base = 0;
 157 }
 158
 159 #ifdef CONFIG_LCD_INFO
 160 #include <nand.h>
 161 #include <version.h>
 162
 163 void lcd_show_board_info(void)
 164 {
 165         ulong dram_size, nand_size;
 166         int i;
 167         char temp[32];
 168
 169         lcd_printf ("%s\n", U_BOOT_VERSION);
 170         lcd_printf ("(C) 2008 ATMEL Corp\n");
 171         lcd_printf ("at91support@atmel.com\n");
 172         lcd_printf ("%s CPU at %s MHz\n",
 173                 AT91_CPU_NAME,
 174                 strmhz(temp, AT91_CPU_CLOCK));
 175
 176         dram_size = 0;
 177         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 178                 dram_size += gd->bd->bi_dram[i].size;
 179         nand_size = 0;
 180         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 181                 nand_size += nand_info[i].size;
 182         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 183                 dram_size >> 20,
 184                 nand_size >> 20 );
 185 }
 186 #endif /* CONFIG_LCD_INFO */
 187 #endif
 188
 189
 190 int board_init(void)
 191 {
 192         /* Enable Ctrlc */
 193         console_init_f();
 194
 195         /* arch number of AT91SAM9RLEK-Board */
 196         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 197         /* adress of boot parameters */
 198         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 199
 200         at91_serial_hw_init();
 201 #ifdef CONFIG_CMD_NAND
 202         at91sam9rlek_nand_hw_init();
 203 #endif
 204 #ifdef CONFIG_HAS_DATAFLASH
 205         at91sam9rlek_spi_hw_init();
 206 #endif
 207 #ifdef CONFIG_LCD
 208         at91sam9rlek_lcd_hw_init();
 209 #endif
 210         return 0;
 211 }
 212
 213 int dram_init(void)
 214 {
 215         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 216         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 217         return 0;
 218 }