board/atmel/atngw100mkii/atngw100mkii.c

   1 /*
   2  * Copyright (C) 2010 Atmel Corporation
   3  *
   4  * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8 #include <common.h>
   9
  10 #include <spi.h>
  11 #include <netdev.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/sdram.h>
  15 #include <asm/arch/clk.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/hmatrix.h>
  18 #include <asm/arch/mmu.h>
  19 #include <asm/arch/portmux.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  24         {
  25                 /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
  26                 .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
  27                 .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
  28                 .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
  29                                         | MMU_VMR_CACHE_NONE,
  30         }, {
  31                 /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
  32                 .virt_pgno      = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
  33                 .nr_pages       = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
  34                 .phys           = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
  35                                         | MMU_VMR_CACHE_NONE,
  36         }, {
  37                 /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
  38                 .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
  39                 .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
  40                 .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
  41                                         | MMU_VMR_CACHE_WRBACK,
  42         },
  43 };
  44
  45 static const struct sdram_config sdram_config = {
  46         .data_bits      = SDRAM_DATA_32BIT,
  47         .row_bits       = 13,
  48         .col_bits       = 10,
  49         .bank_bits      = 2,
  50         .cas            = 3,
  51         .twr            = 2,
  52         .trc            = 7,
  53         .trp            = 2,
  54         .trcd           = 2,
  55         .tras           = 5,
  56         .txsr           = 6,
  57         /* 7.81 us */
  58         .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  59 };
  60
  61 int board_early_init_f(void)
  62 {
  63         /* Enable SDRAM in the EBI mux */
  64         hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
  65                         | HMATRIX_BIT(EBI_NAND_ENABLE));
  66
  67         portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
  68                         PORTMUX_DRIVE_HIGH);
  69         portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
  70                         PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
  71                         | PORTMUX_DRIVE_MIN);
  72         portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  73
  74 #if defined(CONFIG_MACB)
  75         portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  76         portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  77 #endif
  78 #if defined(CONFIG_MMC)
  79         portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  80 #endif
  81 #if defined(CONFIG_ATMEL_SPI)
  82         portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
  83 #endif
  84
  85         return 0;
  86 }
  87
  88 phys_size_t initdram(int board_type)
  89 {
  90         unsigned long expected_size;
  91         unsigned long actual_size;
  92         void *sdram_base;
  93
  94         sdram_base = uncached(EBI_SDRAM_BASE);
  95
  96         expected_size = sdram_init(sdram_base, &sdram_config);
  97         actual_size = get_ram_size(sdram_base, expected_size);
  98
  99         if (expected_size != actual_size)
 100                 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
 101                                 actual_size >> 20, expected_size >> 20);
 102
 103         return actual_size;
 104 }
 105
 106 int board_early_init_r(void)
 107 {
 108         gd->bd->bi_phy_id[0] = 0x01;
 109         gd->bd->bi_phy_id[1] = 0x03;
 110         return 0;
 111 }
 112
 113 #ifdef CONFIG_CMD_NET
 114 int board_eth_init(bd_t *bi)
 115 {
 116         macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
 117         macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
 118         return 0;
 119 }
 120 #endif
 121
 122 /* SPI chip select control */
 123 #ifdef CONFIG_ATMEL_SPI
 124 #define ATNGW100_DATAFLASH_CS_PIN       GPIO_PIN_PA(3)
 125
 126 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 127 {
 128         return bus == 0 && cs == 0;
 129 }
 130
 131 void spi_cs_activate(struct spi_slave *slave)
 132 {
 133         gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
 134 }
 135
 136 void spi_cs_deactivate(struct spi_slave *slave)
 137 {
 138         gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
 139 }
 140 #endif /* CONFIG_ATMEL_SPI */