2962e0c1f471b9cd61c27a3c390da3ff3524c2df
[karo-tx-uboot.git] / board / bachmann / ot1200 / ot1200.c
1 /*
2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3  * Copyright (C) 2014, Bachmann electronic GmbH
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <malloc.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/imx-common/iomux-v3.h>
15 #include <asm/imx-common/mxc_i2c.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/arch/crm_regs.h>
18 #include <mmc.h>
19 #include <fsl_esdhc.h>
20 #include <netdev.h>
21 #include <i2c.h>
22 #include <pca953x.h>
23 #include <asm/gpio.h>
24 #include <phy.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define OUTPUT_40OHM    (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
29
30 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP |                  \
31         OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32
33 #define USDHC_PAD_CTRL  (PAD_CTL_PUS_47K_UP |                   \
34         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
35         PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37 #define ENET_PAD_CTRL   (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
38         PAD_CTL_HYS)
39
40 #define SPI_PAD_CTRL    (PAD_CTL_HYS | OUTPUT_40OHM |           \
41         PAD_CTL_SRE_FAST)
42
43 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
44         PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
45
46 int dram_init(void)
47 {
48         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
49
50         return 0;
51 }
52
53 static iomux_v3_cfg_t const uart1_pads[] = {
54         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
55         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56 };
57
58 static void setup_iomux_uart(void)
59 {
60         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
61 }
62
63 static iomux_v3_cfg_t const enet_pads[] = {
64         MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
65         MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
66         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
67         MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
68         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
69         MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
70         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
71         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72         MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73         MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
75         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
76         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78         MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79         MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80         MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 };
82
83 static void setup_iomux_enet(void)
84 {
85         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
86 }
87
88 static iomux_v3_cfg_t const ecspi1_pads[] = {
89         MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
90         MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
91         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
92         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
93         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
94 };
95
96 static void setup_iomux_spi(void)
97 {
98         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
99 }
100
101 int board_spi_cs_gpio(unsigned bus, unsigned cs)
102 {
103         return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
104 }
105
106 int board_early_init_f(void)
107 {
108         setup_iomux_uart();
109         setup_iomux_spi();
110
111         return 0;
112 }
113
114 static iomux_v3_cfg_t const usdhc3_pads[] = {
115         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 };
127
128 int board_mmc_getcd(struct mmc *mmc)
129 {
130         return 1;
131 }
132
133 struct fsl_esdhc_cfg usdhc_cfg[] = {
134         {USDHC3_BASE_ADDR},
135 };
136
137 int board_mmc_init(bd_t *bis)
138 {
139         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
140         usdhc_cfg[0].max_bus_width = 8;
141
142         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
143
144         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
145 }
146
147 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
148
149 /* I2C3 - IO expander  */
150 static struct i2c_pads_info i2c_pad_info2 = {
151         .scl = {
152                 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
153                 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
154                 .gp = IMX_GPIO_NR(3, 17)
155         },
156         .sda = {
157                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
158                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
159                 .gp = IMX_GPIO_NR(3, 18)
160         }
161 };
162
163 static iomux_v3_cfg_t const pwm_pad[] = {
164         MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
165 };
166
167 static void leds_on(void)
168 {
169         /* turn on all possible leds connected via GPIO expander */
170         i2c_set_bus_num(2);
171         pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
172         pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
173 }
174
175 static void backlight_lcd_off(void)
176 {
177         unsigned gpio = IMX_GPIO_NR(2, 0);
178         gpio_direction_output(gpio, 0);
179
180         gpio = IMX_GPIO_NR(2, 3);
181         gpio_direction_output(gpio, 0);
182 }
183
184 int board_eth_init(bd_t *bis)
185 {
186         uint32_t base = IMX_FEC_BASE;
187         struct mii_dev *bus = NULL;
188         struct phy_device *phydev = NULL;
189         int ret;
190
191         setup_iomux_enet();
192
193         bus = fec_get_miibus(base, -1);
194         if (!bus)
195                 return 0;
196
197         /* scan phy 0 and 5 */
198         phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
199         if (!phydev) {
200                 free(bus);
201                 return 0;
202         }
203
204         /* depending on the phy address we can detect our board version */
205         if (phydev->addr == 0)
206                 setenv("boardver", "");
207         else
208                 setenv("boardver", "mr");
209
210         printf("using phy at %d\n", phydev->addr);
211         ret = fec_probe(bis, -1, base, bus, phydev);
212         if (ret) {
213                 printf("FEC MXC: %s:failed\n", __func__);
214                 free(phydev);
215                 free(bus);
216         }
217         return 0;
218 }
219
220 int board_init(void)
221 {
222         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
223
224         backlight_lcd_off();
225
226         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
227
228         leds_on();
229
230         /* enable ecspi3 clocks */
231         enable_cspi_clock(1, 2);
232
233         return 0;
234 }
235
236 int checkboard(void)
237 {
238         puts("Board: "CONFIG_SYS_BOARD"\n");
239         return 0;
240 }
241
242 #ifdef CONFIG_CMD_BMODE
243 static const struct boot_mode board_boot_modes[] = {
244         /* 4 bit bus width */
245         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
246         {NULL,          0},
247 };
248 #endif
249
250 int misc_init_r(void)
251 {
252 #ifdef CONFIG_CMD_BMODE
253         add_board_boot_modes(board_boot_modes);
254 #endif
255         return 0;
256 }