board/balloon3/balloon3.c

   1 /*
   2  * Balloon3 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <asm/arch/hardware.h>
  24 #include <serial.h>
  25 #include <asm/io.h>
  26 #include <spartan3.h>
  27 #include <command.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 void balloon3_init_fpga(void);
  32
  33 /*
  34  * Miscelaneous platform dependent initialisations
  35  */
  36
  37 int board_init(void)
  38 {
  39         /* arch number of vpac270 */
  40         gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
  41
  42         /* adress of boot parameters */
  43         gd->bd->bi_boot_params = 0xa0000100;
  44
  45         /* Init the FPGA */
  46         balloon3_init_fpga();
  47
  48         return 0;
  49 }
  50
  51 struct serial_device *default_serial_console(void)
  52 {
  53         return &serial_stuart_device;
  54 }
  55
  56 int dram_init(void)
  57 {
  58         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  59         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  60         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  61
  62         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  63         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  64         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  65
  66         return 0;
  67 }
  68
  69 #ifdef  CONFIG_CMD_USB
  70 int usb_board_init(void)
  71 {
  72         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  73                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  74                 UHCHR);
  75
  76         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  77
  78         while (readl(UHCHR) & UHCHR_FSBIR)
  79                 ;
  80
  81         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  82         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  83
  84         /* Clear any OTG Pin Hold */
  85         if (readl(PSSR) & PSSR_OTGPH)
  86                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  87
  88         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  89         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  90
  91         /* Set port power control mask bits, only 3 ports. */
  92         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  93
  94         /* enable port 2 */
  95         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  96                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  97
  98         return 0;
  99 }
 100
 101 void usb_board_init_fail(void)
 102 {
 103         return;
 104 }
 105
 106 void usb_board_stop(void)
 107 {
 108         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 109         udelay(11);
 110         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 111
 112         writel(readl(UHCCOMS) | 1, UHCCOMS);
 113         udelay(10);
 114
 115         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 116
 117         return;
 118 }
 119 #endif
 120
 121 #if defined(CONFIG_FPGA)
 122 /* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
 123 int fpga_pgm_fn(int nassert, int nflush, int cookie)
 124 {
 125         if (nassert)
 126                 writel(0x80, GPCR3);
 127         else
 128                 writel(0x80, GPSR3);
 129         if (nflush)
 130                 writel(0x100, GPCR3);
 131         else
 132                 writel(0x100, GPSR3);
 133         return nassert;
 134 }
 135
 136 /* Check GPIO83 -- INITB */
 137 int fpga_init_fn(int cookie)
 138 {
 139         return !(readl(GPLR2) & 0x80000);
 140 }
 141
 142 /* Check GPIO84 -- BUSY */
 143 int fpga_busy_fn(int cookie)
 144 {
 145         return !(readl(GPLR2) & 0x100000);
 146 }
 147
 148 /* Check GPIO111 -- DONE */
 149 int fpga_done_fn(int cookie)
 150 {
 151         return readl(GPLR3) & 0x8000;
 152 }
 153
 154 /* Configure GPIO104 as GPIO and deassert it */
 155 int fpga_pre_config_fn(int cookie)
 156 {
 157         writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
 158         writel(0x100, GPCR3);
 159         return 0;
 160 }
 161
 162 /* Configure GPIO104 as nSKTSEL */
 163 int fpga_post_config_fn(int cookie)
 164 {
 165         writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
 166         return 0;
 167 }
 168
 169 /* Toggle RDnWR */
 170 int fpga_wr_fn(int nassert_write, int flush, int cookie)
 171 {
 172         udelay(1000);
 173
 174         if (nassert_write)
 175                 writel(0x100, GPCR3);
 176         else
 177                 writel(0x100, GPSR3);
 178
 179         return nassert_write;
 180 }
 181
 182 /* Write program to the FPGA */
 183 int fpga_wdata_fn(uchar data, int flush, int cookie)
 184 {
 185         writeb(data, 0x10f00000);
 186         return 0;
 187 }
 188
 189 /* Toggle Clock pin -- NO-OP */
 190 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 191 {
 192         return assert_clk;
 193 }
 194
 195 /* Toggle ChipSelect pin -- NO-OP */
 196 int fpga_cs_fn(int assert_clk, int flush, int cookie)
 197 {
 198         return assert_clk;
 199 }
 200
 201 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
 202         fpga_pre_config_fn,
 203         fpga_pgm_fn,
 204         fpga_init_fn,
 205         NULL,   /* err */
 206         fpga_done_fn,
 207         fpga_clk_fn,
 208         fpga_cs_fn,
 209         fpga_wr_fn,
 210         NULL,   /* rdata */
 211         fpga_wdata_fn,
 212         fpga_busy_fn,
 213         NULL,   /* abort */
 214         fpga_post_config_fn,
 215 };
 216
 217 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
 218                         (void *)&balloon3_fpga_fns, 0);
 219
 220 /* Initialize the FPGA */
 221 void balloon3_init_fpga(void)
 222 {
 223         fpga_init();
 224         fpga_add(fpga_xilinx, &fpga);
 225 }
 226 #else
 227 void balloon3_init_fpga(void) {}
 228 #endif /* CONFIG_FPGA */