b6c8791f0486fb7d6fe101c9e399ab2e77cea840
[karo-tx-uboot.git] / board / calao / sbc35_a9g20 / sbc35_a9g20.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Copyright (C) 2009
7  * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <asm/arch/at91sam9260_matrix.h>
31 #include <asm/arch/at91sam9_smc.h>
32 #include <asm/arch/at91_common.h>
33 #include <asm/arch/at91_pmc.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/gpio.h>
36
37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
38 #include <net.h>
39 #endif
40 #include <netdev.h>
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 /* ------------------------------------------------------------------------- */
45 /*
46  * Miscelaneous platform dependent initialisations
47  */
48
49 #ifdef CONFIG_CMD_NAND
50 static void sbc35_a9g20_nand_hw_init(void)
51 {
52         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
53         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
54         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
55         unsigned long csa;
56
57         /* Enable CS3 */
58         csa = readl(&matrix->ebicsa);
59         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
60         writel(csa, &matrix->ebicsa);
61
62         /* Configure SMC CS3 for NAND/SmartMedia */
63         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
64                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
65                 &smc->cs[3].setup);
66         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
67                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
68                 &smc->cs[3].pulse);
69         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
70                 &smc->cs[3].cycle);
71         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
72                 AT91_SMC_MODE_EXNW_DISABLE |
73 #ifdef CONFIG_SYS_NAND_DBW_16
74                 AT91_SMC_MODE_DBW_16 |
75 #else /* CONFIG_SYS_NAND_DBW_8 */
76                 AT91_SMC_MODE_DBW_8 |
77 #endif
78                 AT91_SMC_MODE_TDF_CYCLE(2),
79                 &smc->cs[3].mode);
80
81         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
82
83         /* Configure RDY/BSY */
84         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
85
86         /* Enable NandFlash */
87         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
88 }
89 #endif
90
91 #ifdef CONFIG_MACB
92 static void sbc35_a9g20_macb_hw_init(void)
93 {
94         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
95         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
96         struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
97         unsigned long erstl;
98
99         /* Enable EMAC clock */
100         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
101
102         /*
103          * Disable pull-up on:
104          *      RXDV (PA17) => PHY normal mode (not Test mode)
105          *      ERX0 (PA14) => PHY ADDR0
106          *      ERX1 (PA15) => PHY ADDR1
107          *      ERX2 (PA25) => PHY ADDR2
108          *      ERX3 (PA26) => PHY ADDR3
109          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
110          *
111          * PHY has internal pull-down
112          */
113         writel(pin_to_mask(AT91_PIN_PA14) |
114                pin_to_mask(AT91_PIN_PA15) |
115                pin_to_mask(AT91_PIN_PA17) |
116                pin_to_mask(AT91_PIN_PA25) |
117                pin_to_mask(AT91_PIN_PA26) |
118                pin_to_mask(AT91_PIN_PA28),
119                &pioa->pudr);
120
121         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
122
123         /* Need to reset PHY -> 500ms reset */
124         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
125                 AT91_RSTC_MR_URSTEN, &rstc->mr);
126
127         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
128
129         /* Wait for end hardware reset */
130         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
131                 ;
132
133         /* Restore NRST value */
134         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
135                 &rstc->mr);
136
137         /* Re-enable pull-up */
138         writel(pin_to_mask(AT91_PIN_PA14) |
139                pin_to_mask(AT91_PIN_PA15) |
140                pin_to_mask(AT91_PIN_PA17) |
141                pin_to_mask(AT91_PIN_PA25) |
142                pin_to_mask(AT91_PIN_PA26) |
143                pin_to_mask(AT91_PIN_PA28),
144                &pioa->puer);
145
146         at91_macb_hw_init();
147 }
148 #endif
149
150 int board_init(void)
151 {
152         /* Enable Ctrlc */
153         console_init_f();
154
155         /* adress of boot parameters */
156         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
157
158         at91_seriald_hw_init();
159         sbc35_a9g20_nand_hw_init();
160 #ifdef CONFIG_ATMEL_SPI
161         at91_spi0_hw_init(1 << 4 | 1 << 5);
162 #endif
163 #ifdef CONFIG_MACB
164         sbc35_a9g20_macb_hw_init();
165 #endif
166
167         return 0;
168 }
169
170 int dram_init(void)
171 {
172         gd->ram_size = get_ram_size(
173                 (void *)CONFIG_SYS_SDRAM_BASE,
174                 CONFIG_SYS_SDRAM_SIZE);
175         return 0;
176 }
177
178 #ifdef CONFIG_RESET_PHY_R
179 void reset_phy(void)
180 {
181 }
182 #endif
183
184 int board_eth_init(bd_t *bis)
185 {
186         int rc = 0;
187 #ifdef CONFIG_MACB
188         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
189 #endif
190         return rc;
191 }