board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <fsl_esdhc.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <fdt_support.h>
  16 #include <sata.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/sata.h>
  22 #include <asm/io.h>
  23 #include <asm/gpio.h>
  24 #include "common.h"
  25 #include "../common/eeprom.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_DWC_AHSATA
  30 static int cm_fx6_issd_gpios[] = {
  31         /* The order of the GPIOs in the array is important! */
  32         CM_FX6_SATA_PHY_SLP,
  33         CM_FX6_SATA_NRSTDLY,
  34         CM_FX6_SATA_PWREN,
  35         CM_FX6_SATA_NSTANDBY1,
  36         CM_FX6_SATA_NSTANDBY2,
  37         CM_FX6_SATA_LDO_EN,
  38 };
  39
  40 static void cm_fx6_sata_power(int on)
  41 {
  42         int i;
  43
  44         if (!on) { /* tell the iSSD that the power will be removed */
  45                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  46                 mdelay(10);
  47         }
  48
  49         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  50                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
  51                 udelay(100);
  52         }
  53
  54         if (!on) /* for compatibility lower the power loss interrupt */
  55                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  56 }
  57
  58 static iomux_v3_cfg_t const sata_pads[] = {
  59         /* SATA PWR */
  60         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  61         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  62         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  63         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  64         /* SATA CTRL */
  65         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  66         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  67         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  68         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  70 };
  71
  72 static void cm_fx6_setup_issd(void)
  73 {
  74         SETUP_IOMUX_PADS(sata_pads);
  75         /* Make sure this gpio has logical 0 value */
  76         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  77         udelay(100);
  78
  79         cm_fx6_sata_power(0);
  80         mdelay(250);
  81         cm_fx6_sata_power(1);
  82 }
  83
  84 #define CM_FX6_SATA_INIT_RETRIES        10
  85 int sata_initialize(void)
  86 {
  87         int err, i;
  88
  89         cm_fx6_setup_issd();
  90         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
  91                 err = setup_sata();
  92                 if (err) {
  93                         printf("SATA setup failed: %d\n", err);
  94                         return err;
  95                 }
  96
  97                 udelay(100);
  98
  99                 err = __sata_initialize();
 100                 if (!err)
 101                         break;
 102
 103                 /* There is no device on the SATA port */
 104                 if (sata_port_status(0, 0) == 0)
 105                         break;
 106
 107                 /* There's a device, but link not established. Retry */
 108         }
 109
 110         return err;
 111 }
 112 #endif
 113
 114 #ifdef CONFIG_SYS_I2C_MXC
 115 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 116                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 117                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 118
 119 I2C_PADS(i2c0_pads,
 120          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 121          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 122          IMX_GPIO_NR(3, 21),
 123          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 124          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 125          IMX_GPIO_NR(3, 28));
 126
 127 I2C_PADS(i2c1_pads,
 128          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 129          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 130          IMX_GPIO_NR(4, 12),
 131          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 132          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 133          IMX_GPIO_NR(4, 13));
 134
 135 I2C_PADS(i2c2_pads,
 136          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 137          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 138          IMX_GPIO_NR(1, 3),
 139          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 140          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 141          IMX_GPIO_NR(1, 6));
 142
 143
 144 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 145 {
 146         int ret;
 147
 148         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 149         if (ret)
 150                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 151
 152         return ret;
 153 }
 154
 155 static int cm_fx6_setup_i2c(void)
 156 {
 157         int ret = 0, err;
 158
 159         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 160         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 161         if (err)
 162                 ret = err;
 163         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 164         if (err)
 165                 ret = err;
 166         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 167         if (err)
 168                 ret = err;
 169
 170         return ret;
 171 }
 172 #else
 173 static int cm_fx6_setup_i2c(void) { return 0; }
 174 #endif
 175
 176 #ifdef CONFIG_USB_EHCI_MX6
 177 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 178                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 179                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 180
 181 static int cm_fx6_usb_hub_reset(void)
 182 {
 183         int err;
 184
 185         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 186         if (err) {
 187                 printf("USB hub rst gpio request failed: %d\n", err);
 188                 return -1;
 189         }
 190
 191         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 192         gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 193         udelay(10);
 194         gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 195         mdelay(1);
 196
 197         return 0;
 198 }
 199
 200 static int cm_fx6_init_usb_otg(void)
 201 {
 202         int ret;
 203         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 204
 205         ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 206         if (ret) {
 207                 printf("USB OTG pwr gpio request failed: %d\n", ret);
 208                 return ret;
 209         }
 210
 211         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 212         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 213                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 214         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 215         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 216         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 217 }
 218
 219 #define MX6_USBNC_BASEADDR      0x2184800
 220 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 221 int board_ehci_hcd_init(int port)
 222 {
 223         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 224
 225         switch (port) {
 226         case 0:
 227                 return cm_fx6_init_usb_otg();
 228         case 1:
 229                 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
 230                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 231
 232                 /* Set PWR polarity to match power switch's enable polarity */
 233                 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 234                 return cm_fx6_usb_hub_reset();
 235         default:
 236                 break;
 237         }
 238
 239         return 0;
 240 }
 241
 242 int board_ehci_power(int port, int on)
 243 {
 244         if (port == 0)
 245                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 246
 247         return 0;
 248 }
 249 #endif
 250
 251 #ifdef CONFIG_FEC_MXC
 252 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 253                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 254
 255 static int mx6_rgmii_rework(struct phy_device *phydev)
 256 {
 257         unsigned short val;
 258
 259         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 260          * which cause ethernet link down/up issue, so disable SmartEEE
 261          */
 262         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 263         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 264         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 265         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 266         val &= ~(0x1 << 8);
 267         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 268
 269         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 270         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 271         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 272         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 273
 274         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 275         val &= 0xffe3;
 276         val |= 0x18;
 277         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 278
 279         /* introduce tx clock delay */
 280         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 281         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 282         val |= 0x0100;
 283         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 284
 285         return 0;
 286 }
 287
 288 int board_phy_config(struct phy_device *phydev)
 289 {
 290         mx6_rgmii_rework(phydev);
 291
 292         if (phydev->drv->config)
 293                 return phydev->drv->config(phydev);
 294
 295         return 0;
 296 }
 297
 298 static iomux_v3_cfg_t const enet_pads[] = {
 299         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 300         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 301         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 302         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 303         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 304         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 305         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 306         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 307         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 308         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 309         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 310         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 311         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 312         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 313         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 314         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 315                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 316         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 317                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 318         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 319                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 320 };
 321
 322 static int handle_mac_address(void)
 323 {
 324         unsigned char enetaddr[6];
 325         int rc;
 326
 327         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 328         if (rc)
 329                 return 0;
 330
 331         rc = cl_eeprom_read_mac_addr(enetaddr);
 332         if (rc)
 333                 return rc;
 334
 335         if (!is_valid_ether_addr(enetaddr))
 336                 return -1;
 337
 338         return eth_setenv_enetaddr("ethaddr", enetaddr);
 339 }
 340
 341 int board_eth_init(bd_t *bis)
 342 {
 343         int res = handle_mac_address();
 344         if (res)
 345                 puts("No MAC address found\n");
 346
 347         SETUP_IOMUX_PADS(enet_pads);
 348         /* phy reset */
 349         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 350         udelay(500);
 351         gpio_set_value(CM_FX6_ENET_NRST, 1);
 352         enable_enet_clk(1);
 353         return cpu_eth_init(bis);
 354 }
 355 #endif
 356
 357 #ifdef CONFIG_NAND_MXS
 358 static iomux_v3_cfg_t const nand_pads[] = {
 359         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 360         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 361         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 362         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 363         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 364         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 365         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 366         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 367         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 368         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 369         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 370         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 371         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 372         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 373 };
 374
 375 static void cm_fx6_setup_gpmi_nand(void)
 376 {
 377         SETUP_IOMUX_PADS(nand_pads);
 378         /* Enable clock roots */
 379         enable_usdhc_clk(1, 3);
 380         enable_usdhc_clk(1, 4);
 381
 382         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 383                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 384                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 385 }
 386 #else
 387 static void cm_fx6_setup_gpmi_nand(void) {}
 388 #endif
 389
 390 #ifdef CONFIG_FSL_ESDHC
 391 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 392         {USDHC1_BASE_ADDR},
 393         {USDHC2_BASE_ADDR},
 394         {USDHC3_BASE_ADDR},
 395 };
 396
 397 static enum mxc_clock usdhc_clk[3] = {
 398         MXC_ESDHC_CLK,
 399         MXC_ESDHC2_CLK,
 400         MXC_ESDHC3_CLK,
 401 };
 402
 403 int board_mmc_init(bd_t *bis)
 404 {
 405         int i;
 406
 407         cm_fx6_set_usdhc_iomux();
 408         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 409                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 410                 usdhc_cfg[i].max_bus_width = 4;
 411                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 412                 enable_usdhc_clk(1, i);
 413         }
 414
 415         return 0;
 416 }
 417 #endif
 418
 419 #ifdef CONFIG_OF_BOARD_SETUP
 420 void ft_board_setup(void *blob, bd_t *bd)
 421 {
 422         uint8_t enetaddr[6];
 423
 424         /* MAC addr */
 425         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 426                 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
 427                                      enetaddr, 6, 1);
 428         }
 429 }
 430 #endif
 431
 432 int board_init(void)
 433 {
 434         int ret;
 435
 436         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 437         cm_fx6_setup_gpmi_nand();
 438
 439         /* Warn on failure but do not abort boot */
 440         ret = cm_fx6_setup_i2c();
 441         if (ret)
 442                 printf("Warning: I2C setup failed: %d\n", ret);
 443
 444         return 0;
 445 }
 446
 447 int checkboard(void)
 448 {
 449         puts("Board: CM-FX6\n");
 450         return 0;
 451 }
 452
 453 void dram_init_banksize(void)
 454 {
 455         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 456         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 457
 458         switch (gd->ram_size) {
 459         case 0x10000000: /* DDR_16BIT_256MB */
 460                 gd->bd->bi_dram[0].size = 0x10000000;
 461                 gd->bd->bi_dram[1].size = 0;
 462                 break;
 463         case 0x20000000: /* DDR_32BIT_512MB */
 464                 gd->bd->bi_dram[0].size = 0x20000000;
 465                 gd->bd->bi_dram[1].size = 0;
 466                 break;
 467         case 0x40000000:
 468                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 469                         gd->bd->bi_dram[0].size = 0x20000000;
 470                         gd->bd->bi_dram[1].size = 0x20000000;
 471                 } else { /* DDR_64BIT_1GB */
 472                         gd->bd->bi_dram[0].size = 0x40000000;
 473                         gd->bd->bi_dram[1].size = 0;
 474                 }
 475                 break;
 476         case 0x80000000: /* DDR_64BIT_2GB */
 477                 gd->bd->bi_dram[0].size = 0x40000000;
 478                 gd->bd->bi_dram[1].size = 0x40000000;
 479                 break;
 480         case 0xEFF00000: /* DDR_64BIT_4GB */
 481                 gd->bd->bi_dram[0].size = 0x70000000;
 482                 gd->bd->bi_dram[1].size = 0x7FF00000;
 483                 break;
 484         }
 485 }
 486
 487 int dram_init(void)
 488 {
 489         gd->ram_size = imx_ddr_size();
 490         switch (gd->ram_size) {
 491         case 0x10000000:
 492         case 0x20000000:
 493         case 0x40000000:
 494         case 0x80000000:
 495                 break;
 496         case 0xF0000000:
 497                 gd->ram_size -= 0x100000;
 498                 break;
 499         default:
 500                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 501                 return -1;
 502         }
 503
 504         return 0;
 505 }
 506
 507 u32 get_board_rev(void)
 508 {
 509         return cl_eeprom_get_board_rev();
 510 }
 511