board/esd/apc405/apc405.c

   1 /*
   2  * (C) Copyright 2005-2008
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2003
   6  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <command.h>
  15 #include <malloc.h>
  16 #include <flash.h>
  17 #include <mtd/cfi_flash.h>
  18 #include <asm/4xx_pci.h>
  19 #include <pci.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #undef FPGA_DEBUG
  24
  25 extern void lxt971_no_sleep(void);
  26
  27 /* fpga configuration data - gzip compressed and generated by bin2c */
  28 const unsigned char fpgadata[] =
  29 {
  30 #include "fpgadata.c"
  31 };
  32
  33 /*
  34  * include common fpga code (for esd boards)
  35  */
  36 #include "../common/fpga.c"
  37
  38 #ifdef CONFIG_LCD_USED
  39 /* logo bitmap data - gzip compressed and generated by bin2c */
  40 unsigned char logo_bmp[] =
  41 {
  42 #include "logo_640_480_24bpp.c"
  43 };
  44
  45 /*
  46  * include common lcd code (for esd boards)
  47  */
  48 #include "../common/lcd.c"
  49 #include "../common/s1d13505_640_480_16bpp.h"
  50 #include "../common/s1d13806_640_480_16bpp.h"
  51 #endif /* CONFIG_LCD_USED */
  52
  53 /*
  54  * include common auto-update code (for esd boards)
  55  */
  56 #include "../common/auto_update.h"
  57
  58 au_image_t au_image[] = {
  59         {"preinst.img", 0, -1, AU_SCRIPT},
  60         {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
  61         {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
  62         {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
  63         {"work.img", 0xfe500000, 0x01400000, AU_NOR},
  64         {"data.img", 0xff900000, 0x00580000, AU_NOR},
  65         {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
  66         {"postinst.img", 0, 0, AU_SCRIPT},
  67 };
  68
  69 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
  70
  71 int board_revision(void)
  72 {
  73         unsigned long CPC0_CR0Reg;
  74         unsigned long value;
  75
  76         /*
  77          * Get version of APC405 board from GPIO's
  78          */
  79
  80         /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
  81         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  82         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
  83         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
  84         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
  85
  86         /* wait some time before reading input */
  87         udelay(1000);
  88
  89         /* get config bits */
  90         value = in_be32((void*)GPIO0_IR) & 0x001c0000;
  91         /*
  92          * Restore GPIO settings
  93          */
  94         mtdcr(CPC0_CR0, CPC0_CR0Reg);
  95
  96         switch (value) {
  97         case 0x001c0000:
  98                 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
  99                 return 2;
 100         case 0x000c0000:
 101                 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
 102                 return 3;
 103         case 0x00180000:
 104                 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
 105                 return 6;
 106         case 0x00140000:
 107                 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
 108                 return 8;
 109         default:
 110                 /* should not be reached! */
 111                 return 0;
 112         }
 113 }
 114
 115 int board_early_init_f (void)
 116 {
 117         /*
 118          * First pull fpga-prg pin low, to disable fpga logic
 119          */
 120         out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
 121         out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
 122         out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
 123
 124         /*
 125          * IRQ 0-15  405GP internally generated; active high; level sensitive
 126          * IRQ 16    405GP internally generated; active low; level sensitive
 127          * IRQ 17-24 RESERVED
 128          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 129          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 130          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 131          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 132          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 133          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 134          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 135          */
 136         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 137         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
 138         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
 139         mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
 140         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
 141         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
 142         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 143
 144         /*
 145          * EBC Configuration Register: set ready timeout to 512 ebc-clks
 146          */
 147         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 148
 149         /*
 150          * New boards have a single 32MB flash connected to CS0
 151          * instead of two 16MB flashes on CS0+1.
 152          */
 153         if (board_revision() >= 8) {
 154                 /* disable CS1 */
 155                 mtebc(PB1AP, 0);
 156                 mtebc(PB1CR, 0);
 157
 158                 /* resize CS0 to 32MB */
 159                 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
 160                 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
 161         }
 162
 163         return 0;
 164 }
 165
 166 int board_early_init_r(void)
 167 {
 168         if (gd->board_type >= 8)
 169                 cfi_flash_num_flash_banks = 1;
 170
 171         return 0;
 172 }
 173
 174 #define FUJI_BASE    0xf0100200
 175 #define LCDBL_PWM    0xa0
 176 #define LCDBL_PWMMIN 0xa4
 177 #define LCDBL_PWMMAX 0xa8
 178
 179 int misc_init_r(void)
 180 {
 181         u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 182         u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
 183         u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
 184         u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
 185         unsigned char *dst;
 186         ulong len = sizeof(fpgadata);
 187         int status;
 188         int index;
 189         int i;
 190         unsigned long CPC0_CR0Reg;
 191         char *str;
 192         uchar *logo_addr;
 193         ulong logo_size;
 194         ushort minb, maxb;
 195         int result;
 196
 197         /*
 198          * Setup GPIO pins (CS6+CS7 as GPIO)
 199          */
 200         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 201         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 202
 203         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 204         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 205                 printf("GUNZIP ERROR - must RESET board to recover\n");
 206                 do_reset(NULL, 0, 0, NULL);
 207         }
 208
 209         status = fpga_boot(dst, len);
 210         if (status != 0) {
 211                 printf("\nFPGA: Booting failed ");
 212                 switch (status) {
 213                 case ERROR_FPGA_PRG_INIT_LOW:
 214                         printf("(Timeout: "
 215                                "INIT not low after asserting PROGRAM*)\n ");
 216                         break;
 217                 case ERROR_FPGA_PRG_INIT_HIGH:
 218                         printf("(Timeout: "
 219                                "INIT not high after deasserting PROGRAM*)\n ");
 220                         break;
 221                 case ERROR_FPGA_PRG_DONE:
 222                         printf("(Timeout: "
 223                                "DONE not high after programming FPGA)\n ");
 224                         break;
 225                 }
 226
 227                 /* display infos on fpgaimage */
 228                 index = 15;
 229                 for (i = 0; i < 4; i++) {
 230                         len = dst[index];
 231                         printf("FPGA: %s\n", &(dst[index+1]));
 232                         index += len + 3;
 233                 }
 234                 putc('\n');
 235                 /* delayed reboot */
 236                 for (i = 20; i > 0; i--) {
 237                         printf("Rebooting in %2d seconds \r",i);
 238                         for (index = 0; index < 1000; index++)
 239                                 udelay(1000);
 240                 }
 241                 putc('\n');
 242                 do_reset(NULL, 0, 0, NULL);
 243         }
 244
 245         /* restore gpio/cs settings */
 246         mtdcr(CPC0_CR0, CPC0_CR0Reg);
 247
 248         puts("FPGA:  ");
 249
 250         /* display infos on fpgaimage */
 251         index = 15;
 252         for (i = 0; i < 4; i++) {
 253                 len = dst[index];
 254                 printf("%s ", &(dst[index + 1]));
 255                 index += len + 3;
 256         }
 257         putc('\n');
 258
 259         free(dst);
 260
 261         /*
 262          * Reset FPGA via FPGA_DATA pin
 263          */
 264         SET_FPGA(FPGA_PRG | FPGA_CLK);
 265         udelay(1000); /* wait 1ms */
 266         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 267         udelay(1000); /* wait 1ms */
 268
 269         /*
 270          * Write board revision in FPGA
 271          */
 272         out_be16(fpga_ctrl2,
 273                  (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
 274
 275         /*
 276          * Enable power on PS/2 interface (with reset)
 277          */
 278         out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 279         for (i=0;i<100;i++)
 280                 udelay(1000);
 281         udelay(1000);
 282         out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 283
 284         /*
 285          * Enable interrupts in exar duart mcr[3]
 286          */
 287         out_8(duart0_mcr, 0x08);
 288         out_8(duart1_mcr, 0x08);
 289
 290         /*
 291          * Init lcd interface and display logo
 292          */
 293         str = getenv("splashimage");
 294         if (str) {
 295                 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
 296                 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 297         } else {
 298                 logo_addr = logo_bmp;
 299                 logo_size = sizeof(logo_bmp);
 300         }
 301
 302         if (gd->board_type >= 6) {
 303                 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 304                                   (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 305                                   regs_13505_640_480_16bpp,
 306                                   sizeof(regs_13505_640_480_16bpp) /
 307                                   sizeof(regs_13505_640_480_16bpp[0]),
 308                                   logo_addr, logo_size);
 309                 if (result && str) {
 310                         /* retry with internal image */
 311                         logo_addr = logo_bmp;
 312                         logo_size = sizeof(logo_bmp);
 313                         lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 314                                  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 315                                  regs_13505_640_480_16bpp,
 316                                  sizeof(regs_13505_640_480_16bpp) /
 317                                  sizeof(regs_13505_640_480_16bpp[0]),
 318                                  logo_addr, logo_size);
 319                 }
 320         } else {
 321                 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 322                                   (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 323                                   regs_13806_640_480_16bpp,
 324                                   sizeof(regs_13806_640_480_16bpp) /
 325                                   sizeof(regs_13806_640_480_16bpp[0]),
 326                                   logo_addr, logo_size);
 327                 if (result && str) {
 328                         /* retry with internal image */
 329                         logo_addr = logo_bmp;
 330                         logo_size = sizeof(logo_bmp);
 331                         lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 332                                  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 333                                  regs_13806_640_480_16bpp,
 334                                  sizeof(regs_13806_640_480_16bpp) /
 335                                  sizeof(regs_13806_640_480_16bpp[0]),
 336                                  logo_addr, logo_size);
 337                 }
 338         }
 339
 340         /*
 341          * Reset microcontroller and setup backlight PWM controller
 342          */
 343         out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
 344         for (i=0;i<10;i++)
 345                 udelay(1000);
 346         out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
 347
 348         minb = 0;
 349         maxb = 0xff;
 350         str = getenv("lcdbl");
 351         if (str) {
 352                 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
 353                 if (str && (*str=',')) {
 354                         str++;
 355                         maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
 356                 } else
 357                         minb = 0;
 358
 359                 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
 360                 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
 361
 362                 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
 363         }
 364         out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
 365
 366         /*
 367          * fix environment for field updated units
 368          */
 369         if (getenv("altbootcmd") == NULL) {
 370                 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
 371                 setenv("usbargs", CONFIG_SYS_USB_ARGS);
 372                 setenv("bootcmd", CONFIG_BOOTCOMMAND);
 373                 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
 374                 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
 375                 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
 376                 saveenv();
 377         }
 378
 379         return (0);
 380 }
 381
 382 /*
 383  * Check Board Identity:
 384  */
 385 int checkboard (void)
 386 {
 387         char str[64];
 388         int i = getenv_f("serial#", str, sizeof(str));
 389
 390         puts ("Board: ");
 391
 392         if (i == -1) {
 393                 puts ("### No HW ID - assuming APC405");
 394         } else {
 395                 puts(str);
 396         }
 397
 398         gd->board_type = board_revision();
 399         printf(", Rev. 1.%ld\n", gd->board_type);
 400
 401         return 0;
 402 }
 403
 404 #ifdef CONFIG_IDE_RESET
 405 void ide_set_reset(int on)
 406 {
 407         u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 408
 409         /*
 410          * Assert or deassert CompactFlash Reset Pin
 411          */
 412         if (on) {
 413                 out_be16(fpga_mode,
 414                          in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 415         } else {
 416                 out_be16(fpga_mode,
 417                          in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 418         }
 419 }
 420 #endif /* CONFIG_IDE_RESET */
 421
 422 void reset_phy(void)
 423 {
 424         /*
 425          * Disable sleep mode in LXT971
 426          */
 427         lxt971_no_sleep();
 428 }
 429
 430 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 431 int usb_board_init(void)
 432 {
 433         return 0;
 434 }
 435
 436 int usb_board_stop(void)
 437 {
 438         unsigned short tmp;
 439         int i;
 440
 441         /*
 442          * reset PCI bus
 443          * This is required to make some very old Linux OHCI driver
 444          * work after U-Boot has used the OHCI controller.
 445          */
 446         pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
 447         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
 448
 449         for (i = 0; i < 100; i++)
 450                 udelay(1000);
 451
 452         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
 453         return 0;
 454 }
 455
 456 int usb_board_init_fail(void)
 457 {
 458         usb_board_stop();
 459         return 0;
 460 }
 461 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */