3 * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
18 puts ("Board: KVME080\n");
22 unsigned long setdram(int m, int row, int col, int bank)
25 unsigned long start, end;
27 uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
28 uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
31 CONFIG_READ_WORD(MCCR1, mccr1);
34 start = CONFIG_SYS_SDRAM_BASE;
35 end = start + (1 << (col + row + 3) ) * bank - 1;
37 for (i = 0; i < m; i++) {
38 mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
40 msar1 |= ((start >> 20) & 0xff) << i * 8;
41 emsar1 |= ((start >> 28) & 0xff) << i * 8;
42 mear1 |= ((end >> 20) & 0xff) << i * 8;
43 emear1 |= ((end >> 28) & 0xff) << i * 8;
45 msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
46 emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
47 mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
48 emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
51 start += (1 << (col + row + 3) ) * bank;
52 end += (1 << (col + row + 3) ) * bank;
56 msar1 |= 0xff << i * 8;
57 emsar1 |= 0x30 << i * 8;
58 mear1 |= 0xff << i * 8;
59 emear1 |= 0x30 << i * 8;
61 msar2 |= 0xff << (i-4) * 8;
62 emsar2 |= 0x30 << (i-4) * 8;
63 mear2 |= 0xff << (i-4) * 8;
64 emear2 |= 0x30 << (i-4) * 8;
68 CONFIG_WRITE_WORD(MCCR1, mccr1);
69 CONFIG_WRITE_WORD(MSAR1, msar1);
70 CONFIG_WRITE_WORD(EMSAR1, emsar1);
71 CONFIG_WRITE_WORD(MEAR1, mear1);
72 CONFIG_WRITE_WORD(EMEAR1, emear1);
73 CONFIG_WRITE_WORD(MSAR2, msar2);
74 CONFIG_WRITE_WORD(EMSAR2, emsar2);
75 CONFIG_WRITE_WORD(MEAR2, mear2);
76 CONFIG_WRITE_WORD(EMEAR2, emear2);
77 CONFIG_WRITE_BYTE(MBER, mber);
79 return (1 << (col + row + 3) ) * bank * m;
82 phys_size_t initdram(int board_type)
88 mtmsr(msr & ~(MSR_IR | MSR_DR));
89 mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
90 mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
91 mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
92 mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
95 if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
96 size = 0x20000000; /* 512MB */
97 else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
98 size = 0x10000000; /* 256MB */
99 else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
100 size = 0x10000000; /* 256MB */
101 else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
102 size = 0x08000000; /* 128MB */
103 else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
104 size = 0x08000000; /* 128MB */
105 else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
106 size = 0x04000000; /* 64MB */
109 mtmsr(msr & ~(MSR_IR | MSR_DR));
110 mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
111 mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
112 mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
113 mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
119 struct pci_controller hose;
121 void pci_init_board(void)
123 pci_mpc824x_init(&hose);
126 int board_early_init_f(void)
128 *(volatile unsigned char *)(0xff080120) = 0xfb;
133 int board_early_init_r(void)
137 CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
138 CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
139 CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
142 mtmsr(msr & ~(MSR_IR | MSR_DR));
143 mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
144 mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
145 mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
146 mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
152 extern int multiverse_init(void);
154 int misc_init_r(void)
160 void *nvram_read(void *dest, const long src, size_t count)
162 volatile uchar *d = (volatile uchar*) dest;
163 volatile uchar *s = (volatile uchar*) src;
166 asm volatile("sync");
171 void nvram_write(long dest, const void *src, size_t count)
173 volatile uchar *d = (volatile uchar*)dest;
174 volatile uchar *s = (volatile uchar*)src;
177 asm volatile("sync");
181 int board_eth_init(bd_t *bis)
183 return pci_eth_init(bis);