2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/errno.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
23 #include "../common/qixis.h"
24 #include "../common/vsc3316_3308.h"
25 #include "../common/idt8t49n222a_serdes_clk.h"
27 #include "b4860qds_qixis.h"
28 #include "b4860qds_crossbar_con.h"
30 #define CLK_MUX_SEL_MASK 0x4
31 #define ETH_PHY_CLK_OUT 0x4
33 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *const freq[] = {"100", "125", "156.25", "161.13",
41 "122.88", "122.88", "122.88"};
44 printf("Board: %sQDS, ", cpu->name);
45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
46 QIXIS_READ(id), QIXIS_READ(arch));
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank: %d\n", sw);
53 else if (sw >= 0x8 && sw <= 0xE)
56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
58 printf("FPGA: v%d (%s), build %d",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor());
61 /* the timestamp string contains "\n" at the end */
62 printf(" on %s", qixis_read_time(buf));
65 * Display the actual SERDES reference clocks as configured by the
66 * dip switches on the board. Note that the SWx registers could
67 * technically be set to force the reference clocks to match the
68 * values that the SERDES expects (or vice versa). For now, however,
69 * we just display both values and hope the user notices when they
72 puts("SERDES Reference Clocks: ");
73 sw = QIXIS_READ(brdcfg[2]);
74 clock = (sw >> 5) & 7;
75 printf("Bank1=%sMHz ", freq[clock]);
76 sw = QIXIS_READ(brdcfg[4]);
77 clock = (sw >> 6) & 3;
78 printf("Bank2=%sMHz\n", freq[clock]);
83 int select_i2c_ch_pca(u8 ch)
87 /* Selecting proper channel via PCA*/
88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
90 printf("PCA: failed to select proper channel.\n");
97 int configure_vsc3316_3308(void)
99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 unsigned int num_vsc16_con, num_vsc08_con;
101 u32 serdes1_prtcl, serdes2_prtcl;
104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
106 if (!serdes1_prtcl) {
107 printf("SERDES1 is not enabled\n");
110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
115 if (!serdes2_prtcl) {
116 printf("SERDES2 is not enabled\n");
119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
122 switch (serdes1_prtcl) {
132 * Lanes: C,D,E,F,G,H: CPRI
134 debug("Configuring crossbar to use onboard SGMII PHYs:"
135 "srds_prctl:%x\n", serdes1_prtcl);
136 num_vsc16_con = NUM_CON_VSC3316;
137 /* Configure VSC3316 crossbar switch */
138 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
140 ret = vsc3316_config(VSC3316_TX_ADDRESS,
141 vsc16_tx_4sfp_sgmii_12_56,
145 ret = vsc3316_config(VSC3316_RX_ADDRESS,
146 vsc16_rx_4sfp_sgmii_12_56,
179 * Lanes: E,F,G,H: CPRI
181 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
182 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
183 num_vsc16_con = NUM_CON_VSC3316;
184 /* Configure VSC3316 crossbar switch */
185 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
187 ret = vsc3316_config(VSC3316_TX_ADDRESS,
188 vsc16_tx_sfp_sgmii_aurora,
192 ret = vsc3316_config(VSC3316_RX_ADDRESS,
193 vsc16_rx_sfp_sgmii_aurora,
202 #ifdef CONFIG_PPC_B4420
208 * Lanes: A,B,C,D: SGMII
209 * Lanes: E,F,G,H: CPRI
211 debug("Configuring crossbar to use onboard SGMII PHYs:"
212 "srds_prctl:%x\n", serdes1_prtcl);
213 num_vsc16_con = NUM_CON_VSC3316;
214 /* Configure VSC3316 crossbar switch */
215 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
217 ret = vsc3316_config(VSC3316_TX_ADDRESS,
218 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
221 ret = vsc3316_config(VSC3316_RX_ADDRESS,
222 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
235 num_vsc16_con = NUM_CON_VSC3316;
236 /* Configure VSC3316 crossbar switch */
237 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
239 ret = vsc3316_config(VSC3316_TX_ADDRESS,
240 vsc16_tx_sfp, num_vsc16_con);
243 ret = vsc3316_config(VSC3316_RX_ADDRESS,
244 vsc16_rx_sfp, num_vsc16_con);
252 printf("WARNING:VSC crossbars programming not supported for:%x"
253 " SerDes1 Protocol.\n", serdes1_prtcl);
257 switch (serdes2_prtcl) {
266 num_vsc08_con = NUM_CON_VSC3308;
267 /* Configure VSC3308 crossbar switch */
268 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
270 ret = vsc3308_config(VSC3308_TX_ADDRESS,
271 vsc08_tx_amc, num_vsc08_con);
274 ret = vsc3308_config(VSC3308_RX_ADDRESS,
275 vsc08_rx_amc, num_vsc08_con);
283 printf("WARNING:VSC crossbars programming not supported for: %x"
284 " SerDes2 Protocol.\n", serdes2_prtcl);
291 int config_serdes1_refclks(void)
293 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
294 serdes_corenet_t *srds_regs =
295 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
296 u32 serdes1_prtcl, lane;
297 unsigned int flag_sgmii_aurora_prtcl = 0;
301 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
302 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
303 if (!serdes1_prtcl) {
304 printf("SERDES1 is not enabled\n");
307 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
308 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
310 /* To prevent generation of reset request from SerDes
311 * while changing the refclks, By setting SRDS_RST_MSK bit,
312 * SerDes reset event cannot cause a reset request
314 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
316 /* Reconfigure IDT idt8t49n222a device for CPRI to work
317 * For this SerDes1's Refclk1 and refclk2 need to be set
320 switch (serdes1_prtcl) {
344 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
345 " for srds_prctl:%x\n", serdes1_prtcl);
346 ret = select_i2c_ch_pca(I2C_CH_IDT);
348 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
349 SERDES_REFCLK_122_88,
350 SERDES_REFCLK_122_88, 0);
352 printf("IDT8T49N222A configuration failed.\n");
355 debug("IDT8T49N222A configured.\n");
359 select_i2c_ch_pca(I2C_CH_DEFAULT);
361 /* Change SerDes1's Refclk1 to 125MHz for on board
362 * SGMIIs or Aurora to work
364 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
365 enum srds_prtcl lane_prtcl = serdes_get_prtcl
366 (0, serdes1_prtcl, lane);
367 switch (lane_prtcl) {
368 case SGMII_FM1_DTSEC1:
369 case SGMII_FM1_DTSEC2:
370 case SGMII_FM1_DTSEC3:
371 case SGMII_FM1_DTSEC4:
372 case SGMII_FM1_DTSEC5:
373 case SGMII_FM1_DTSEC6:
375 flag_sgmii_aurora_prtcl++;
382 if (flag_sgmii_aurora_prtcl)
383 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
385 /* Steps For SerDes PLLs reset and reconfiguration after
386 * changing SerDes's refclks
388 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
389 debug("For PLL%d reset and reconfiguration after"
390 " changing refclks\n", i+1);
391 clrbits_be32(&srds_regs->bank[i].rstctl,
392 SRDS_RSTCTL_SDRST_B);
394 clrbits_be32(&srds_regs->bank[i].rstctl,
395 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
397 setbits_be32(&srds_regs->bank[i].rstctl,
399 setbits_be32(&srds_regs->bank[i].rstctl,
400 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
401 | SRDS_RSTCTL_SDRST_B));
405 printf("WARNING:IDT8T49N222A configuration not"
406 " supported for:%x SerDes1 Protocol.\n",
411 /* Clearing SRDS_RST_MSK bit as now
412 * SerDes reset event can cause a reset request
414 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
418 int config_serdes2_refclks(void)
420 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
421 serdes_corenet_t *srds2_regs =
422 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
427 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
428 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
429 if (!serdes2_prtcl) {
430 debug("SERDES2 is not enabled\n");
433 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
434 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
436 /* To prevent generation of reset request from SerDes
437 * while changing the refclks, By setting SRDS_RST_MSK bit,
438 * SerDes reset event cannot cause a reset request
440 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
442 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
443 * For this SerDes2's Refclk1 need to be set to 100MHz
445 switch (serdes2_prtcl) {
449 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
451 ret = select_i2c_ch_pca(I2C_CH_IDT);
453 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
455 SERDES_REFCLK_156_25, 0);
457 printf("IDT8T49N222A configuration failed.\n");
460 debug("IDT8T49N222A configured.\n");
464 select_i2c_ch_pca(I2C_CH_DEFAULT);
466 /* Steps For SerDes PLLs reset and reconfiguration after
467 * changing SerDes's refclks
469 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
470 clrbits_be32(&srds2_regs->bank[i].rstctl,
471 SRDS_RSTCTL_SDRST_B);
473 clrbits_be32(&srds2_regs->bank[i].rstctl,
474 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
476 setbits_be32(&srds2_regs->bank[i].rstctl,
478 setbits_be32(&srds2_regs->bank[i].rstctl,
479 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
480 | SRDS_RSTCTL_SDRST_B));
484 printf("IDT configuration not supported for:%x S2 Protocol.\n",
489 /* Clearing SRDS_RST_MSK bit as now
490 * SerDes reset event can cause a reset request
492 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
496 int board_early_init_r(void)
498 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
499 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
503 * Remap Boot flash + PROMJET region to caching-inhibited
504 * so that flash can be erased properly.
507 /* Flush d-cache and invalidate i-cache of any FLASH data */
511 /* invalidate existing TLB entry for flash + promjet */
512 disable_tlb(flash_esel);
514 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
515 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
516 0, flash_esel, BOOKE_PAGESZ_256M, 1);
519 #ifdef CONFIG_SYS_DPAA_QBMAN
522 /* SerDes1 refclks need to be set again, as default clks
523 * are not suitable for CPRI and onboard SGMIIs to work
525 * This function will set SerDes1's Refclk1 and refclk2
526 * as per SerDes1 protocols
528 if (config_serdes1_refclks())
529 printf("SerDes1 Refclks couldn't set properly.\n");
531 printf("SerDes1 Refclks have been set.\n");
533 /* SerDes2 refclks need to be set again, as default clks
534 * are not suitable for PCIe SATA to work
535 * This function will set SerDes2's Refclk1 and refclk2
536 * for SerDes2 protocols having PCIe in them
537 * for PCIe SATA to work
539 ret = config_serdes2_refclks();
541 printf("SerDes2 Refclks have been set.\n");
542 else if (ret == -ENODEV)
543 printf("SerDes disable, Refclks couldn't change.\n");
545 printf("SerDes2 Refclk reconfiguring failed.\n");
547 /* Configure VSC3316 and VSC3308 crossbar switches */
548 if (configure_vsc3316_3308())
549 printf("VSC:failed to configure VSC3316/3308.\n");
551 printf("VSC:VSC3316/3308 successfully configured.\n");
553 select_i2c_ch_pca(I2C_CH_DEFAULT);
558 unsigned long get_board_sys_clk(void)
560 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
562 switch ((sysclk_conf & 0x0C) >> 2) {
573 unsigned long get_board_ddr_clk(void)
575 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
577 switch (ddrclk_conf & 0x03) {
588 static int serdes_refclock(u8 sw, u8 sdclk)
595 brdcfg4 = QIXIS_READ(brdcfg[4]);
596 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
597 return SRDS_PLLCR0_RFCK_SEL_125;
599 clock = (sw >> 5) & 7;
601 clock = (sw >> 6) & 3;
605 ret = SRDS_PLLCR0_RFCK_SEL_100;
608 ret = SRDS_PLLCR0_RFCK_SEL_125;
611 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
614 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
619 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
629 #define NUM_SRDS_BANKS 2
631 int misc_init_r(void)
634 serdes_corenet_t *srds_regs =
635 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
636 u32 actual[NUM_SRDS_BANKS];
640 sw = QIXIS_READ(brdcfg[2]);
641 clock = serdes_refclock(sw, 1);
645 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
647 sw = QIXIS_READ(brdcfg[4]);
648 clock = serdes_refclock(sw, 2);
652 printf("Warning: SDREFCLK2 switch setting unsupported\n");
654 for (i = 0; i < NUM_SRDS_BANKS; i++) {
655 u32 pllcr0 = srds_regs->bank[i].pllcr0;
656 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
657 if (expected != actual[i]) {
658 printf("Warning: SERDES bank %u expects reference clock"
659 " %sMHz, but actual is %sMHz\n", i + 1,
660 serdes_clock_to_string(expected),
661 serdes_clock_to_string(actual[i]));
668 void ft_board_setup(void *blob, bd_t *bd)
673 ft_cpu_setup(blob, bd);
675 base = getenv_bootm_low();
676 size = getenv_bootm_size();
678 fdt_fixup_memory(blob, (u64)base, (u64)size);
681 pci_of_setup(blob, bd);
684 fdt_fixup_liodn(blob);
686 #ifdef CONFIG_HAS_FSL_DR_USB
687 fdt_fixup_dr_usb(blob, bd);
690 #ifdef CONFIG_SYS_DPAA_FMAN
691 fdt_fixup_fman_ethernet(blob);
692 fdt_fixup_board_enet(blob);
697 * Dump board switch settings.
698 * The bits that cannot be read/sampled via some FPGA or some
699 * registers, they will be displayed as
700 * underscore in binary format. mask[] has those bits.
701 * Some bits are calculated differently than the actual switches
702 * if booting with overriding by FPGA.
704 void qixis_dump_switch(void)
710 * Any bit with 1 means that bit cannot be reverse engineered.
711 * It will be displayed as _ in binary format.
713 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
715 u8 brdcfg[16], dutcfg[16];
717 for (i = 0; i < 16; i++) {
718 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
719 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
722 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
724 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
725 ((dutcfg[2] & 0x07) << 4) | \
726 ((dutcfg[6] & 0x10) >> 1) | \
727 ((dutcfg[6] & 0x80) >> 5) | \
728 ((dutcfg[1] & 0x40) >> 5) | \
732 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
733 ((brdcfg[1] & 0xc0) >> 2) | \
736 puts("DIP switch settings:\n");
737 for (i = 0; i < 5; i++) {
738 printf("SW%d = 0b%s (0x%02x)\n",
739 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);