board/freescale/corenet_ds/eth_p4080.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <netdev.h>
  26 #include <asm/mmu.h>
  27 #include <asm/processor.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_law.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/fsl_serdes.h>
  33 #include <asm/fsl_portals.h>
  34 #include <asm/fsl_liodn.h>
  35 #include <malloc.h>
  36 #include <fm_eth.h>
  37 #include <fsl_mdio.h>
  38 #include <miiphy.h>
  39 #include <phy.h>
  40
  41 #include "../common/ngpixis.h"
  42 #include "../common/fman.h"
  43 #include <asm/fsl_dtsec.h>
  44
  45 #define EMI_NONE        0xffffffff
  46 #define EMI_MASK        0xf0000000
  47 #define EMI1_RGMII      0x0
  48 #define EMI1_SLOT3      0x80000000      /* bank1 EFGH */
  49 #define EMI1_SLOT4      0x40000000      /* bank2 ABCD */
  50 #define EMI1_SLOT5      0xc0000000      /* bank3 ABCD */
  51 #define EMI2_SLOT4      0x10000000      /* bank2 ABCD */
  52 #define EMI2_SLOT5      0x30000000      /* bank3 ABCD */
  53 #define EMI1_MASK       0xc0000000
  54 #define EMI2_MASK       0x30000000
  55
  56 static int mdio_mux[NUM_FM_PORTS];
  57
  58 static char *mdio_names[16] = {
  59         "P4080DS_MDIO0",
  60         "P4080DS_MDIO1",
  61         NULL,
  62         "P4080DS_MDIO3",
  63         "P4080DS_MDIO4",
  64         NULL, NULL, NULL,
  65         "P4080DS_MDIO8",
  66         NULL, NULL, NULL,
  67         "P4080DS_MDIO12",
  68         NULL, NULL, NULL,
  69 };
  70
  71 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
  72 {
  73         return mdio_names[(muxval & EMI_MASK) >> 28];
  74 }
  75
  76 struct mii_dev *mii_dev_for_muxval(u32 muxval)
  77 {
  78         struct mii_dev *bus;
  79         char *name = p4080ds_mdio_name_for_muxval(muxval);
  80
  81         if (!name) {
  82                 printf("No bus for muxval %x\n", muxval);
  83                 return NULL;
  84         }
  85
  86         bus = miiphy_get_dev_by_name(name);
  87
  88         if (!bus) {
  89                 printf("No bus by name %s\n", name);
  90                 return NULL;
  91         }
  92
  93         return bus;
  94 }
  95
  96 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
  97 int board_phy_config(struct phy_device *phydev)
  98 {
  99         if (phydev->drv->uid == PHY_UID_TN2020) {
 100                 unsigned long timeout = 1 * 1000; /* 1 seconds */
 101                 enum srds_prtcl device;
 102
 103                 /*
 104                  * Wait for the XAUI to come out of reset.  This is when it
 105                  * starts transmitting alignment signals.
 106                  */
 107                 while (--timeout) {
 108                         int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
 109                         if (reg < 0) {
 110                                 printf("TN2020: Error reading from PHY at "
 111                                        "address %u\n", phydev->addr);
 112                                 break;
 113                         }
 114                         /*
 115                          * Note that we've never actually seen
 116                          * MDIO_CTRL1_RESET set to 1.
 117                          */
 118                         if ((reg & MDIO_CTRL1_RESET) == 0)
 119                                 break;
 120                         udelay(1000);
 121                 }
 122
 123                 if (!timeout) {
 124                         printf("TN2020: Timeout waiting for PHY at address %u "
 125                                " to reset.\n", phydev->addr);
 126                 }
 127
 128                 switch (phydev->addr) {
 129                 case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
 130                         device = XAUI_FM1;
 131                         break;
 132                 case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
 133                         device = XAUI_FM2;
 134                         break;
 135                 default:
 136                         device = NONE;
 137                 }
 138
 139                 serdes_reset_rx(device);
 140         }
 141
 142         return 0;
 143 }
 144 #endif
 145
 146 struct p4080ds_mdio {
 147         u32 muxval;
 148         struct mii_dev *realbus;
 149 };
 150
 151 static void p4080ds_mux_mdio(u32 muxval)
 152 {
 153         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 154         uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
 155         gpioval |= muxval;
 156
 157         out_be32(&pgpio->gpdat, gpioval);
 158 }
 159
 160 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
 161                                 int regnum)
 162 {
 163         struct p4080ds_mdio *priv = bus->priv;
 164
 165         p4080ds_mux_mdio(priv->muxval);
 166
 167         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 168 }
 169
 170 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
 171                                 int regnum, u16 value)
 172 {
 173         struct p4080ds_mdio *priv = bus->priv;
 174
 175         p4080ds_mux_mdio(priv->muxval);
 176
 177         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 178 }
 179
 180 static int p4080ds_mdio_reset(struct mii_dev *bus)
 181 {
 182         struct p4080ds_mdio *priv = bus->priv;
 183
 184         return priv->realbus->reset(priv->realbus);
 185 }
 186
 187 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
 188 {
 189         struct p4080ds_mdio *pmdio;
 190         struct mii_dev *bus = mdio_alloc();
 191
 192         if (!bus) {
 193                 printf("Failed to allocate P4080DS MDIO bus\n");
 194                 return -1;
 195         }
 196
 197         pmdio = malloc(sizeof(*pmdio));
 198         if (!pmdio) {
 199                 printf("Failed to allocate P4080DS private data\n");
 200                 free(bus);
 201                 return -1;
 202         }
 203
 204         bus->read = p4080ds_mdio_read;
 205         bus->write = p4080ds_mdio_write;
 206         bus->reset = p4080ds_mdio_reset;
 207         sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
 208
 209         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 210
 211         if (!pmdio->realbus) {
 212                 printf("No bus with name %s\n", realbusname);
 213                 free(bus);
 214                 free(pmdio);
 215                 return -1;
 216         }
 217
 218         pmdio->muxval = muxval;
 219         bus->priv = pmdio;
 220
 221         return mdio_register(bus);
 222 }
 223
 224 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 225                                 enum fm_port port, int offset)
 226 {
 227         if (mdio_mux[port] == EMI1_RGMII)
 228                 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
 229
 230         if (mdio_mux[port] == EMI1_SLOT3) {
 231                 int idx = port - FM2_DTSEC1 + 5;
 232                 char phy[16];
 233
 234                 sprintf(phy, "phy%d_slot3", idx);
 235
 236                 fdt_set_phy_handle(blob, prop, pa, phy);
 237         }
 238 }
 239
 240 void fdt_fixup_board_enet(void *fdt)
 241 {
 242         int i;
 243
 244         /*
 245          * P4080DS can be configured in many different ways, supporting a number
 246          * of combinations of ethernet devices and phy types.  In order to
 247          * have just one device tree for all of those configurations, we fix up
 248          * the tree here.  By default, the device tree configures FM1 and FM2
 249          * for SGMII, and configures XAUI on both 10G interfaces.  So we have
 250          * a number of different variables to track:
 251          *
 252          * 1) Whether the device is configured at all.  Whichever devices are
 253          *    not enabled should be disabled by setting the "status" property
 254          *    to "disabled".
 255          * 2) What the PHY interface is.  If this is an RGMII connection,
 256          *    we should change the "phy-connection-type" property to
 257          *    "rgmii"
 258          * 3) Which PHY is being used.  Because the MDIO buses are muxed,
 259          *    we need to redirect the "phy-handle" property to point at the
 260          *    PHY on the right slot/bus.
 261          */
 262
 263         /* We've got six MDIO nodes that may or may not need to exist */
 264         fdt_status_disabled_by_alias(fdt, "emi1_slot3");
 265         fdt_status_disabled_by_alias(fdt, "emi1_slot4");
 266         fdt_status_disabled_by_alias(fdt, "emi1_slot5");
 267         fdt_status_disabled_by_alias(fdt, "emi2_slot4");
 268         fdt_status_disabled_by_alias(fdt, "emi2_slot5");
 269
 270         for (i = 0; i < NUM_FM_PORTS; i++) {
 271                 switch (mdio_mux[i]) {
 272                 case EMI1_SLOT3:
 273                         fdt_status_okay_by_alias(fdt, "emi1_slot3");
 274                         break;
 275                 case EMI1_SLOT4:
 276                         fdt_status_okay_by_alias(fdt, "emi1_slot4");
 277                         break;
 278                 case EMI1_SLOT5:
 279                         fdt_status_okay_by_alias(fdt, "emi1_slot5");
 280                         break;
 281                 case EMI2_SLOT4:
 282                         fdt_status_okay_by_alias(fdt, "emi2_slot4");
 283                         break;
 284                 case EMI2_SLOT5:
 285                         fdt_status_okay_by_alias(fdt, "emi2_slot5");
 286                         break;
 287                 }
 288         }
 289 }
 290
 291 enum board_slots {
 292         SLOT1 = 1,
 293         SLOT2,
 294         SLOT3,
 295         SLOT4,
 296         SLOT5,
 297         SLOT6,
 298 };
 299
 300 int board_eth_init(bd_t *bis)
 301 {
 302 #ifdef CONFIG_FMAN_ENET
 303         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 304         int i;
 305         struct fsl_pq_mdio_info dtsec_mdio_info;
 306         struct tgec_mdio_info tgec_mdio_info;
 307
 308         u8 lane_to_slot[] = {
 309                 SLOT1, /* 0 - Bank 1:A */
 310                 SLOT1, /* 1 - Bank 1:B */
 311                 SLOT2, /* 2 - Bank 1:C */
 312                 SLOT2, /* 3 - Bank 1:D */
 313                 SLOT3, /* 4 - Bank 1:E */
 314                 SLOT3, /* 5 - Bank 1:F */
 315                 SLOT3, /* 6 - Bank 1:G */
 316                 SLOT3, /* 7 - Bank 1:H */
 317                 SLOT6, /* 8 - Bank 1:I */
 318                 SLOT6, /* 9 - Bank 1:J */
 319                 SLOT4, /* 10 - Bank 2:A */
 320                 SLOT4, /* 11 - Bank 2:B */
 321                 SLOT4, /* 12 - Bank 2:C */
 322                 SLOT4, /* 13 - Bank 2:D */
 323                 SLOT5, /* 14 - Bank 3:A */
 324                 SLOT5, /* 15 - Bank 3:B */
 325                 SLOT5, /* 16 - Bank 3:C */
 326                 SLOT5, /* 17 - Bank 3:D */
 327         };
 328
 329         /* Initialize the mdio_mux array so we can recognize empty elements */
 330         for (i = 0; i < NUM_FM_PORTS; i++)
 331                 mdio_mux[i] = EMI_NONE;
 332
 333         /* The first 4 GPIOs are outputs to control MDIO bus muxing */
 334         out_be32(&pgpio->gpdir, EMI_MASK);
 335
 336         dtsec_mdio_info.regs =
 337                 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
 338         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 339
 340         /* Register the 1G MDIO bus */
 341         fsl_pq_mdio_init(bis, &dtsec_mdio_info);
 342
 343         tgec_mdio_info.regs =
 344                 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 345         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 346
 347         /* Register the 10G MDIO bus */
 348         fm_tgec_mdio_init(bis, &tgec_mdio_info);
 349
 350         /* Register the 6 muxing front-ends to the MDIO buses */
 351         p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 352         p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 353         p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 354         p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 355         p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
 356         p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
 357
 358         fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
 359         fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
 360         fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
 361         fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
 362         fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
 363
 364 #if (CONFIG_SYS_NUM_FMAN == 2)
 365         fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
 366         fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
 367         fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
 368         fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
 369         fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
 370 #endif
 371
 372         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 373                 int idx = i - FM1_DTSEC1, lane, slot;
 374                 switch (fm_info_get_enet_if(i)) {
 375                 case PHY_INTERFACE_MODE_SGMII:
 376                         lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
 377                         if (lane < 0)
 378                                 break;
 379                         slot = lane_to_slot[lane];
 380                         switch (slot) {
 381                         case SLOT3:
 382                                 mdio_mux[i] = EMI1_SLOT3;
 383                                 fm_info_set_mdio(i,
 384                                         mii_dev_for_muxval(mdio_mux[i]));
 385                                 break;
 386                         case SLOT4:
 387                                 mdio_mux[i] = EMI1_SLOT4;
 388                                 fm_info_set_mdio(i,
 389                                         mii_dev_for_muxval(mdio_mux[i]));
 390                                 break;
 391                         case SLOT5:
 392                                 mdio_mux[i] = EMI1_SLOT5;
 393                                 fm_info_set_mdio(i,
 394                                         mii_dev_for_muxval(mdio_mux[i]));
 395                                 break;
 396                         };
 397                         break;
 398                 case PHY_INTERFACE_MODE_RGMII:
 399                         fm_info_set_phy_address(i, 0);
 400                         mdio_mux[i] = EMI1_RGMII;
 401                         fm_info_set_mdio(i,
 402                                 mii_dev_for_muxval(mdio_mux[i]));
 403                         break;
 404                 default:
 405                         break;
 406                 }
 407         }
 408
 409         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 410                 int idx = i - FM1_10GEC1, lane, slot;
 411                 switch (fm_info_get_enet_if(i)) {
 412                 case PHY_INTERFACE_MODE_XGMII:
 413                         lane = serdes_get_first_lane(XAUI_FM1 + idx);
 414                         if (lane < 0)
 415                                 break;
 416                         slot = lane_to_slot[lane];
 417                         switch (slot) {
 418                         case SLOT4:
 419                                 mdio_mux[i] = EMI2_SLOT4;
 420                                 fm_info_set_mdio(i,
 421                                         mii_dev_for_muxval(mdio_mux[i]));
 422                                 break;
 423                         case SLOT5:
 424                                 mdio_mux[i] = EMI2_SLOT5;
 425                                 fm_info_set_mdio(i,
 426                                         mii_dev_for_muxval(mdio_mux[i]));
 427                                 break;
 428                         };
 429                         break;
 430                 default:
 431                         break;
 432                 }
 433         }
 434
 435 #if (CONFIG_SYS_NUM_FMAN == 2)
 436         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 437                 int idx = i - FM2_DTSEC1, lane, slot;
 438                 switch (fm_info_get_enet_if(i)) {
 439                 case PHY_INTERFACE_MODE_SGMII:
 440                         lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
 441                         if (lane < 0)
 442                                 break;
 443                         slot = lane_to_slot[lane];
 444                         switch (slot) {
 445                         case SLOT3:
 446                                 mdio_mux[i] = EMI1_SLOT3;
 447                                 fm_info_set_mdio(i,
 448                                         mii_dev_for_muxval(mdio_mux[i]));
 449                                 break;
 450                         case SLOT4:
 451                                 mdio_mux[i] = EMI1_SLOT4;
 452                                 fm_info_set_mdio(i,
 453                                         mii_dev_for_muxval(mdio_mux[i]));
 454                                 break;
 455                         case SLOT5:
 456                                 mdio_mux[i] = EMI1_SLOT5;
 457                                 fm_info_set_mdio(i,
 458                                         mii_dev_for_muxval(mdio_mux[i]));
 459                                 break;
 460                         };
 461                         break;
 462                 case PHY_INTERFACE_MODE_RGMII:
 463                         fm_info_set_phy_address(i, 0);
 464                         mdio_mux[i] = EMI1_RGMII;
 465                         fm_info_set_mdio(i,
 466                                 mii_dev_for_muxval(mdio_mux[i]));
 467                         break;
 468                 default:
 469                         break;
 470                 }
 471         }
 472
 473         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 474                 int idx = i - FM2_10GEC1, lane, slot;
 475                 switch (fm_info_get_enet_if(i)) {
 476                 case PHY_INTERFACE_MODE_XGMII:
 477                         lane = serdes_get_first_lane(XAUI_FM2 + idx);
 478                         if (lane < 0)
 479                                 break;
 480                         slot = lane_to_slot[lane];
 481                         switch (slot) {
 482                         case SLOT4:
 483                                 mdio_mux[i] = EMI2_SLOT4;
 484                                 fm_info_set_mdio(i,
 485                                         mii_dev_for_muxval(mdio_mux[i]));
 486                                 break;
 487                         case SLOT5:
 488                                 mdio_mux[i] = EMI2_SLOT5;
 489                                 fm_info_set_mdio(i,
 490                                         mii_dev_for_muxval(mdio_mux[i]));
 491                                 break;
 492                         };
 493                         break;
 494                 default:
 495                         break;
 496                 }
 497         }
 498 #endif
 499
 500         cpu_eth_init(bis);
 501 #endif /* CONFIG_FMAN_ENET */
 502
 503         return pci_eth_init(bis);
 504 }