2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/fsl_pci.h>
29 #include <asm/fsl_ddr_sdram.h>
33 #include <fdt_support.h>
34 #include <spd_sdram.h>
37 #include "../common/pixis.h"
39 void sdram_init(void);
40 phys_size_t fixed_sdram(void);
41 void mpc8610hpcd_diu_init(void);
44 /* called before any console output */
45 int board_early_init_f(void)
47 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
48 volatile ccsr_gur_t *gur = &immap->im_gur;
50 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
58 u8 *pixis_base = (u8 *)PIXIS_BASE;
60 /*Do not use 8259PIC*/
61 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
62 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
64 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
65 version = in_8(pixis_base + PIXIS_PVER);
67 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
68 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
71 /* Using this for DIU init before the driver in linux takes over
72 * Enable the TFP410 Encoder (I2C address 0x38)
76 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
77 /* Verify if enabled */
79 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
80 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
83 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
84 /* Verify if enabled */
86 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
87 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
89 #ifdef CONFIG_FSL_DIU_FB
90 mpc8610hpcd_diu_init();
98 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
99 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
100 u8 *pixis_base = (u8 *)PIXIS_BASE;
102 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
103 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
104 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
105 in_8(pixis_base + PIXIS_PVER));
107 mcm->abcr |= 0x00010000; /* 0 */
108 mcm->hpmr3 = 0x80000008; /* 4c */
120 initdram(int board_type)
122 phys_size_t dram_size = 0;
124 #if defined(CONFIG_SPD_EEPROM)
125 dram_size = fsl_ddr_sdram();
127 dram_size = fixed_sdram();
130 #if defined(CONFIG_SYS_RAMBOOT)
140 #if !defined(CONFIG_SPD_EEPROM)
142 * Fixed sdram init -- doesn't use serial presence detect.
145 phys_size_t fixed_sdram(void)
147 #if !defined(CONFIG_SYS_RAMBOOT)
148 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
149 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
152 ddr->cs0_bnds = 0x0000001f;
153 ddr->cs0_config = 0x80010202;
155 ddr->timing_cfg_3 = 0x00000000;
156 ddr->timing_cfg_0 = 0x00260802;
157 ddr->timing_cfg_1 = 0x3935d322;
158 ddr->timing_cfg_2 = 0x14904cc8;
159 ddr->sdram_mode = 0x00480432;
160 ddr->sdram_mode_2 = 0x00000000;
161 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
162 ddr->sdram_data_init = 0xDEADBEEF;
163 ddr->sdram_clk_cntl = 0x03800000;
164 ddr->sdram_cfg_2 = 0x04400010;
166 #if defined(CONFIG_DDR_ECC)
167 ddr->err_int_en = 0x0000000d;
168 ddr->err_disable = 0x00000000;
169 ddr->err_sbe = 0x00010000;
175 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
178 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
180 debug("DDR - 1st controller: memory initializing\n");
182 * Poll until memory is initialized.
183 * 512 Meg at 400 might hit this 200 times or so.
185 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
188 debug("DDR: memory initialized\n\n");
193 return 512 * 1024 * 1024;
195 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
200 #if defined(CONFIG_PCI)
202 * Initialize PCI Devices, report devices found.
205 #ifndef CONFIG_PCI_PNP
206 static struct pci_config_table pci_fsl86xxads_config_table[] = {
207 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
208 PCI_IDSEL_NUMBER, PCI_ANY_ID,
209 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
211 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
217 static struct pci_controller pci1_hose = {
218 #ifndef CONFIG_PCI_PNP
219 config_table:pci_mpc86xxcts_config_table
222 #endif /* CONFIG_PCI */
225 static struct pci_controller pcie1_hose;
229 static struct pci_controller pcie2_hose;
232 int first_free_busno = 0;
234 void pci_init_board(void)
236 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
237 volatile ccsr_gur_t *gur = &immap->im_gur;
238 uint devdisr = gur->devdisr;
239 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
240 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
241 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
242 >> MPC8610_PORBMSR_HA_SHIFT;
244 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
245 devdisr, io_sel, host_agent);
249 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
250 struct pci_controller *hose = &pcie1_hose;
251 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
252 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
253 struct pci_region *r = hose->regions;
255 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
256 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
257 pcie_ep ? "End Point" : "Root Complex",
259 if (pci->pme_msg_det)
260 pci->pme_msg_det = 0xffffffff;
262 /* outbound memory */
264 CONFIG_SYS_PCIE1_MEM_BUS,
265 CONFIG_SYS_PCIE1_MEM_PHYS,
266 CONFIG_SYS_PCIE1_MEM_SIZE,
271 CONFIG_SYS_PCIE1_IO_BUS,
272 CONFIG_SYS_PCIE1_IO_PHYS,
273 CONFIG_SYS_PCIE1_IO_SIZE,
276 hose->region_count = r - hose->regions;
278 hose->first_busno = first_free_busno;
280 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
282 first_free_busno = hose->last_busno + 1;
283 printf(" PCI-Express 1 on bus %02x - %02x\n",
284 hose->first_busno, hose->last_busno);
287 puts(" PCI-Express 1: Disabled\n");
290 puts("PCI-Express 1: Disabled\n");
291 #endif /* CONFIG_PCIE1 */
296 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
297 struct pci_controller *hose = &pcie2_hose;
298 struct pci_region *r = hose->regions;
300 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
301 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
303 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
304 printf(" PCI-Express 2 connected to slot as %s" \
305 " (base address %x)\n",
306 pcie_ep ? "End Point" : "Root Complex",
308 if (pci->pme_msg_det)
309 pci->pme_msg_det = 0xffffffff;
311 /* outbound memory */
313 CONFIG_SYS_PCIE2_MEM_BUS,
314 CONFIG_SYS_PCIE2_MEM_PHYS,
315 CONFIG_SYS_PCIE2_MEM_SIZE,
320 CONFIG_SYS_PCIE2_IO_BUS,
321 CONFIG_SYS_PCIE2_IO_PHYS,
322 CONFIG_SYS_PCIE2_IO_SIZE,
325 hose->region_count = r - hose->regions;
327 hose->first_busno = first_free_busno;
329 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
331 first_free_busno = hose->last_busno + 1;
332 printf(" PCI-Express 2 on bus %02x - %02x\n",
333 hose->first_busno, hose->last_busno);
335 puts(" PCI-Express 2: Disabled\n");
338 puts("PCI-Express 2: Disabled\n");
339 #endif /* CONFIG_PCIE2 */
344 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
345 struct pci_controller *hose = &pci1_hose;
346 int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
347 struct pci_region *r = hose->regions;
349 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
350 printf(" PCI connected to PCI slots as %s" \
351 " (base address %x)\n",
352 pci_agent ? "Agent" : "Host",
355 /* outbound memory */
357 CONFIG_SYS_PCI1_MEM_BUS,
358 CONFIG_SYS_PCI1_MEM_PHYS,
359 CONFIG_SYS_PCI1_MEM_SIZE,
364 CONFIG_SYS_PCI1_IO_BUS,
365 CONFIG_SYS_PCI1_IO_PHYS,
366 CONFIG_SYS_PCI1_IO_SIZE,
369 hose->region_count = r - hose->regions;
371 hose->first_busno = first_free_busno;
373 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
375 first_free_busno = hose->last_busno + 1;
376 printf(" PCI on bus %02x - %02x\n",
377 hose->first_busno, hose->last_busno);
381 puts(" PCI: Disabled\n");
383 #endif /* CONFIG_PCI1 */
386 #if defined(CONFIG_OF_BOARD_SETUP)
388 ft_board_setup(void *blob, bd_t *bd)
390 ft_cpu_setup(blob, bd);
393 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
396 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
399 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
406 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
410 get_board_sys_clk(ulong dummy)
414 u8 *pixis_base = (u8 *)PIXIS_BASE;
416 i = in_8(pixis_base + PIXIS_SPD);
449 int board_eth_init(bd_t *bis)
451 return pci_eth_init(bis);
454 void board_reset(void)
456 u8 *pixis_base = (u8 *)PIXIS_BASE;
458 out_8(pixis_base + PIXIS_RST, 0);