board/freescale/mx53loco/mx53loco.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   3  * Jason Liu <r64343@freescale.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/mx5x_pins.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/iomux.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/errno.h>
  34 #include <netdev.h>
  35 #include <i2c.h>
  36 #include <mmc.h>
  37 #include <fsl_esdhc.h>
  38 #include <asm/gpio.h>
  39 #include <pmic.h>
  40 #include <dialog_pmic.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 int dram_init(void)
  45 {
  46         u32 size1, size2;
  47
  48         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  49         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  50
  51         gd->ram_size = size1 + size2;
  52
  53         return 0;
  54 }
  55 void dram_init_banksize(void)
  56 {
  57         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  58         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  59
  60         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  61         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  62 }
  63
  64 static void setup_iomux_uart(void)
  65 {
  66         /* UART1 RXD */
  67         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  68         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  69                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  70                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  71                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  72                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  73         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  74
  75         /* UART1 TXD */
  76         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  77         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  78                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  79                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  80                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  81                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  82 }
  83
  84 #ifdef CONFIG_USB_EHCI_MX5
  85 int board_ehci_hcd_init(int port)
  86 {
  87         /* request VBUS power enable pin, GPIO[8}, gpio7 */
  88         mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
  89         gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
  90         gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
  91         return 0;
  92 }
  93 #endif
  94
  95 static void setup_iomux_fec(void)
  96 {
  97         /*FEC_MDIO*/
  98         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
  99         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 100                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 101                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 102                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 103         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 104
 105         /*FEC_MDC*/
 106         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 107         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 108
 109         /* FEC RXD1 */
 110         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 111         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 112                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 113
 114         /* FEC RXD0 */
 115         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 116         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 117                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 118
 119          /* FEC TXD1 */
 120         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 121         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 122
 123         /* FEC TXD0 */
 124         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 125         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 126
 127         /* FEC TX_EN */
 128         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 129         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 130
 131         /* FEC TX_CLK */
 132         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 133         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 134                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 135
 136         /* FEC RX_ER */
 137         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 138         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 139                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 140
 141         /* FEC CRS */
 142         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 143         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 144                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 145 }
 146
 147 #ifdef CONFIG_FSL_ESDHC
 148 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 149         {MMC_SDHC1_BASE_ADDR, 1},
 150         {MMC_SDHC3_BASE_ADDR, 1},
 151 };
 152
 153 int board_mmc_getcd(struct mmc *mmc)
 154 {
 155         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 156         int ret;
 157
 158         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 159         gpio_direction_input(75);
 160         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 161         gpio_direction_input(77);
 162
 163         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 164                 ret = !gpio_get_value(77); /* GPIO3_13 */
 165         else
 166                 ret = !gpio_get_value(75); /* GPIO3_11 */
 167
 168         return ret;
 169 }
 170
 171 int board_mmc_init(bd_t *bis)
 172 {
 173         u32 index;
 174         s32 status = 0;
 175
 176         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 177                 switch (index) {
 178                 case 0:
 179                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 180                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 181                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 182                                                 IOMUX_CONFIG_ALT0);
 183                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 184                                                 IOMUX_CONFIG_ALT0);
 185                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 186                                                 IOMUX_CONFIG_ALT0);
 187                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 188                                                 IOMUX_CONFIG_ALT0);
 189                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 190                                                 IOMUX_CONFIG_ALT1);
 191
 192                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 193                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 194                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 195                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 196                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 197                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 198                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 199                                 PAD_CTL_DRV_HIGH);
 200                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 201                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 202                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 203                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 204                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 205                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 206                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 207                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 208                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 209                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 210                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 211                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 212                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 213                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 214                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 215                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 216                         break;
 217                 case 1:
 218                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 219                                                 IOMUX_CONFIG_ALT2);
 220                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 221                                                 IOMUX_CONFIG_ALT2);
 222                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 223                                                 IOMUX_CONFIG_ALT4);
 224                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 225                                                 IOMUX_CONFIG_ALT4);
 226                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 227                                                 IOMUX_CONFIG_ALT4);
 228                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 229                                                 IOMUX_CONFIG_ALT4);
 230                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 231                                                 IOMUX_CONFIG_ALT4);
 232                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 233                                                 IOMUX_CONFIG_ALT4);
 234                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 235                                                 IOMUX_CONFIG_ALT4);
 236                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 237                                                 IOMUX_CONFIG_ALT4);
 238                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 239                                                 IOMUX_CONFIG_ALT1);
 240
 241                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 242                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 243                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 244                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 245                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 246                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 247                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 248                                 PAD_CTL_DRV_HIGH);
 249                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 250                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 251                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 252                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 253                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 254                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 255                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 256                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 257                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 258                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 259                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 260                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 261                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 262                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 263                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 264                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 265                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 266                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 267                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 268                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 269                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 270                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 271                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 272                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 273                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 274                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 275                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 276                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 277                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 278                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 279                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 280                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 281
 282                         break;
 283                 default:
 284                         printf("Warning: you configured more ESDHC controller"
 285                                 "(%d) as supported by the board(2)\n",
 286                                 CONFIG_SYS_FSL_ESDHC_NUM);
 287                         return status;
 288                 }
 289                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 290         }
 291
 292         return status;
 293 }
 294 #endif
 295
 296 static void setup_iomux_i2c(void)
 297 {
 298         /* I2C1 SDA */
 299         mxc_request_iomux(MX53_PIN_CSI0_D8,
 300                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
 301         mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
 302                 INPUT_CTL_PATH0);
 303         mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
 304                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 305                 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
 306                 PAD_CTL_PUE_PULL |
 307                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 308         /* I2C1 SCL */
 309         mxc_request_iomux(MX53_PIN_CSI0_D9,
 310                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
 311         mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
 312                 INPUT_CTL_PATH0);
 313         mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
 314                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 315                 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
 316                 PAD_CTL_PUE_PULL |
 317                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 318 }
 319
 320 static int power_init(void)
 321 {
 322         unsigned int val, ret;
 323         struct pmic *p;
 324
 325         pmic_init();
 326         p = get_pmic();
 327
 328         /* Set VDDA to 1.25V */
 329         val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
 330         ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
 331
 332         ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
 333         val |= DA9052_SUPPLY_VBCOREGO;
 334         ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
 335
 336         /* Set Vcc peripheral to 1.35V */
 337         ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
 338         ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
 339
 340         return ret;
 341 }
 342
 343 static void clock_1GHz(void)
 344 {
 345         int ret;
 346         u32 ref_clk = CONFIG_SYS_MX5_HCLK;
 347         /*
 348          * After increasing voltage to 1.25V, we can switch
 349          * CPU clock to 1GHz and DDR to 400MHz safely
 350          */
 351         ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
 352         if (ret)
 353                 printf("CPU:   Switch CPU clock to 1GHZ failed\n");
 354
 355         ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
 356         ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
 357         if (ret)
 358                 printf("CPU:   Switch DDR clock to 400MHz failed\n");
 359 }
 360
 361 int board_early_init_f(void)
 362 {
 363         setup_iomux_uart();
 364         setup_iomux_fec();
 365
 366         return 0;
 367 }
 368
 369 int print_cpuinfo(void)
 370 {
 371         u32 cpurev;
 372
 373         cpurev = get_cpu_rev();
 374         printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
 375                 (cpurev & 0xFF000) >> 12,
 376                 (cpurev & 0x000F0) >> 4,
 377                 (cpurev & 0x0000F) >> 0,
 378                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 379         printf("Reset cause: %s\n", get_reset_cause());
 380         return 0;
 381 }
 382
 383 #ifdef CONFIG_BOARD_LATE_INIT
 384 int board_late_init(void)
 385 {
 386         setup_iomux_i2c();
 387         if (!power_init())
 388                 clock_1GHz();
 389         print_cpuinfo();
 390
 391         return 0;
 392 }
 393 #endif
 394
 395 int board_init(void)
 396 {
 397         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 398
 399         mxc_set_sata_internal_clock();
 400
 401         return 0;
 402 }
 403
 404 int checkboard(void)
 405 {
 406         puts("Board: MX53 LOCO\n");
 407
 408         return 0;
 409 }