board/freescale/mx6qsabrelite/mx6qsabrelite.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6q_pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/imx-common/mxc_i2c.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc.h>
  20 #include <malloc.h>
  21 #include <micrel.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <linux/fb.h>
  25 #include <ipu_pixfmt.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <i2c.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  33         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  34         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  37         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42
  43 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  44         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  45
  46 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  51         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  56
  57         return 0;
  58 }
  59
  60 iomux_v3_cfg_t const uart1_pads[] = {
  61         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  63 };
  64
  65 iomux_v3_cfg_t const uart2_pads[] = {
  66         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  67         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  68 };
  69
  70 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  71
  72 /* I2C1, SGTL5000 */
  73 struct i2c_pads_info i2c_pad_info0 = {
  74         .scl = {
  75                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  76                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
  77                 .gp = IMX_GPIO_NR(3, 21)
  78         },
  79         .sda = {
  80                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  81                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
  82                 .gp = IMX_GPIO_NR(3, 28)
  83         }
  84 };
  85
  86 /* I2C2 Camera, MIPI */
  87 struct i2c_pads_info i2c_pad_info1 = {
  88         .scl = {
  89                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  90                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
  91                 .gp = IMX_GPIO_NR(4, 12)
  92         },
  93         .sda = {
  94                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  95                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
  96                 .gp = IMX_GPIO_NR(4, 13)
  97         }
  98 };
  99
 100 /* I2C3, J15 - RGB connector */
 101 struct i2c_pads_info i2c_pad_info2 = {
 102         .scl = {
 103                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 104                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
 105                 .gp = IMX_GPIO_NR(1, 5)
 106         },
 107         .sda = {
 108                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 109                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
 110                 .gp = IMX_GPIO_NR(7, 11)
 111         }
 112 };
 113
 114 iomux_v3_cfg_t const usdhc3_pads[] = {
 115         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT5__GPIO_7_0, /* CD */
 122 };
 123
 124 iomux_v3_cfg_t const usdhc4_pads[] = {
 125         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */
 132 };
 133
 134 iomux_v3_cfg_t const enet_pads1[] = {
 135         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 136         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 137         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 138         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 139         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 140         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 141         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 142         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 143         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 144         /* pin 35 - 1 (PHY_AD2) on reset */
 145         MX6_PAD_RGMII_RXC__GPIO_6_30,
 146         /* pin 32 - 1 - (MODE0) all */
 147         MX6_PAD_RGMII_RD0__GPIO_6_25,
 148         /* pin 31 - 1 - (MODE1) all */
 149         MX6_PAD_RGMII_RD1__GPIO_6_27,
 150         /* pin 28 - 1 - (MODE2) all */
 151         MX6_PAD_RGMII_RD2__GPIO_6_28,
 152         /* pin 27 - 1 - (MODE3) all */
 153         MX6_PAD_RGMII_RD3__GPIO_6_29,
 154         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 155         MX6_PAD_RGMII_RX_CTL__GPIO_6_24,
 156         /* pin 42 PHY nRST */
 157         MX6_PAD_EIM_D23__GPIO_3_23,
 158 };
 159
 160 iomux_v3_cfg_t const enet_pads2[] = {
 161         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167 };
 168
 169 /* Button assignments for J14 */
 170 static iomux_v3_cfg_t const button_pads[] = {
 171         /* Menu */
 172         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 173         /* Back */
 174         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 175         /* Labelled Search (mapped to Power under Android) */
 176         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 177         /* Home */
 178         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 179         /* Volume Down */
 180         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 181         /* Volume Up */
 182         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 183 };
 184
 185 static void setup_iomux_enet(void)
 186 {
 187         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 188         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 189         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 190         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 191         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 192         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 193         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 194         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 195
 196         /* Need delay 10ms according to KSZ9021 spec */
 197         udelay(1000 * 10);
 198         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 199
 200         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 201 }
 202
 203 iomux_v3_cfg_t const usb_pads[] = {
 204         MX6_PAD_GPIO_17__GPIO_7_12,
 205 };
 206
 207 static void setup_iomux_uart(void)
 208 {
 209         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 210         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 211 }
 212
 213 #ifdef CONFIG_USB_EHCI_MX6
 214 int board_ehci_hcd_init(int port)
 215 {
 216         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 217
 218         /* Reset USB hub */
 219         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 220         mdelay(2);
 221         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 222
 223         return 0;
 224 }
 225 #endif
 226
 227 #ifdef CONFIG_FSL_ESDHC
 228 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 229         {USDHC3_BASE_ADDR},
 230         {USDHC4_BASE_ADDR},
 231 };
 232
 233 int board_mmc_getcd(struct mmc *mmc)
 234 {
 235         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 236         int ret;
 237
 238         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 239                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 240                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 241         } else {
 242                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 243                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 244         }
 245
 246         return ret;
 247 }
 248
 249 int board_mmc_init(bd_t *bis)
 250 {
 251         s32 status = 0;
 252         u32 index = 0;
 253
 254         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 255         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 256
 257         usdhc_cfg[0].max_bus_width = 4;
 258         usdhc_cfg[1].max_bus_width = 4;
 259
 260         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 261                 switch (index) {
 262                 case 0:
 263                         imx_iomux_v3_setup_multiple_pads(
 264                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 265                         break;
 266                 case 1:
 267                         imx_iomux_v3_setup_multiple_pads(
 268                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 269                         break;
 270                 default:
 271                         printf("Warning: you configured more USDHC controllers"
 272                                "(%d) then supported by the board (%d)\n",
 273                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 274                         return status;
 275                 }
 276
 277                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 278         }
 279
 280         return status;
 281 }
 282 #endif
 283
 284 #ifdef CONFIG_MXC_SPI
 285 iomux_v3_cfg_t const ecspi1_pads[] = {
 286         /* SS1 */
 287         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 288         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 289         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 290         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 291 };
 292
 293 void setup_spi(void)
 294 {
 295         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 296                                          ARRAY_SIZE(ecspi1_pads));
 297 }
 298 #endif
 299
 300 int board_phy_config(struct phy_device *phydev)
 301 {
 302         /* min rx data delay */
 303         ksz9021_phy_extended_write(phydev,
 304                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 305         /* min tx data delay */
 306         ksz9021_phy_extended_write(phydev,
 307                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 308         /* max rx/tx clock delay, min rx/tx control */
 309         ksz9021_phy_extended_write(phydev,
 310                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 311         if (phydev->drv->config)
 312                 phydev->drv->config(phydev);
 313
 314         return 0;
 315 }
 316
 317 int board_eth_init(bd_t *bis)
 318 {
 319         uint32_t base = IMX_FEC_BASE;
 320         struct mii_dev *bus = NULL;
 321         struct phy_device *phydev = NULL;
 322         int ret;
 323
 324         setup_iomux_enet();
 325
 326 #ifdef CONFIG_FEC_MXC
 327         bus = fec_get_miibus(base, -1);
 328         if (!bus)
 329                 return 0;
 330         /* scan phy 4,5,6,7 */
 331         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 332         if (!phydev) {
 333                 free(bus);
 334                 return 0;
 335         }
 336         printf("using phy at %d\n", phydev->addr);
 337         ret  = fec_probe(bis, -1, base, bus, phydev);
 338         if (ret) {
 339                 printf("FEC MXC: %s:failed\n", __func__);
 340                 free(phydev);
 341                 free(bus);
 342         }
 343 #endif
 344         return 0;
 345 }
 346
 347 static void setup_buttons(void)
 348 {
 349         imx_iomux_v3_setup_multiple_pads(button_pads,
 350                                          ARRAY_SIZE(button_pads));
 351 }
 352
 353 #ifdef CONFIG_CMD_SATA
 354
 355 int setup_sata(void)
 356 {
 357         struct iomuxc_base_regs *const iomuxc_regs
 358                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 359         int ret = enable_sata_clock();
 360         if (ret)
 361                 return ret;
 362
 363         clrsetbits_le32(&iomuxc_regs->gpr[13],
 364                         IOMUXC_GPR13_SATA_MASK,
 365                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 366                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 367                         |IOMUXC_GPR13_SATA_SPEED_3G
 368                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 369                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 370                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 371                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 372                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 373                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 374
 375         return 0;
 376 }
 377 #endif
 378
 379 #if defined(CONFIG_VIDEO_IPUV3)
 380
 381 static iomux_v3_cfg_t const backlight_pads[] = {
 382         /* Backlight on RGB connector: J15 */
 383         MX6_PAD_SD1_DAT3__GPIO_1_21,
 384 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 385
 386         /* Backlight on LVDS connector: J6 */
 387         MX6_PAD_SD1_CMD__GPIO_1_18,
 388 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 389 };
 390
 391 static iomux_v3_cfg_t const rgb_pads[] = {
 392         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 393         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 394         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 395         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 396         MX6_PAD_DI0_PIN4__GPIO_4_20,
 397         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 398         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 399         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 400         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 401         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 402         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 403         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 404         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 405         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 406         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 407         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 408         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 409         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 410         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 411         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 412         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 413         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 414         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 415         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 416         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 417         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 418         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 419         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 420         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 421 };
 422
 423 struct display_info_t {
 424         int     bus;
 425         int     addr;
 426         int     pixfmt;
 427         int     (*detect)(struct display_info_t const *dev);
 428         void    (*enable)(struct display_info_t const *dev);
 429         struct  fb_videomode mode;
 430 };
 431
 432
 433 static int detect_hdmi(struct display_info_t const *dev)
 434 {
 435         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 436         return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 437 }
 438
 439 static void enable_hdmi(struct display_info_t const *dev)
 440 {
 441         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 442         u8 reg;
 443         printf("%s: setup HDMI monitor\n", __func__);
 444         reg = readb(&hdmi->phy_conf0);
 445         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 446         writeb(reg, &hdmi->phy_conf0);
 447
 448         udelay(3000);
 449         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 450         writeb(reg, &hdmi->phy_conf0);
 451         udelay(3000);
 452         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 453         writeb(reg, &hdmi->phy_conf0);
 454         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 455 }
 456
 457 static int detect_i2c(struct display_info_t const *dev)
 458 {
 459         return ((0 == i2c_set_bus_num(dev->bus))
 460                 &&
 461                 (0 == i2c_probe(dev->addr)));
 462 }
 463
 464 static void enable_lvds(struct display_info_t const *dev)
 465 {
 466         struct iomuxc *iomux = (struct iomuxc *)
 467                                 IOMUXC_BASE_ADDR;
 468         u32 reg = readl(&iomux->gpr[2]);
 469         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 470         writel(reg, &iomux->gpr[2]);
 471         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 472 }
 473
 474 static void enable_rgb(struct display_info_t const *dev)
 475 {
 476         imx_iomux_v3_setup_multiple_pads(
 477                 rgb_pads,
 478                  ARRAY_SIZE(rgb_pads));
 479         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 480 }
 481
 482 static struct display_info_t const displays[] = {{
 483         .bus    = -1,
 484         .addr   = 0,
 485         .pixfmt = IPU_PIX_FMT_RGB24,
 486         .detect = detect_hdmi,
 487         .enable = enable_hdmi,
 488         .mode   = {
 489                 .name           = "HDMI",
 490                 .refresh        = 60,
 491                 .xres           = 1024,
 492                 .yres           = 768,
 493                 .pixclock       = 15385,
 494                 .left_margin    = 220,
 495                 .right_margin   = 40,
 496                 .upper_margin   = 21,
 497                 .lower_margin   = 7,
 498                 .hsync_len      = 60,
 499                 .vsync_len      = 10,
 500                 .sync           = FB_SYNC_EXT,
 501                 .vmode          = FB_VMODE_NONINTERLACED
 502 } }, {
 503         .bus    = 2,
 504         .addr   = 0x4,
 505         .pixfmt = IPU_PIX_FMT_LVDS666,
 506         .detect = detect_i2c,
 507         .enable = enable_lvds,
 508         .mode   = {
 509                 .name           = "Hannstar-XGA",
 510                 .refresh        = 60,
 511                 .xres           = 1024,
 512                 .yres           = 768,
 513                 .pixclock       = 15385,
 514                 .left_margin    = 220,
 515                 .right_margin   = 40,
 516                 .upper_margin   = 21,
 517                 .lower_margin   = 7,
 518                 .hsync_len      = 60,
 519                 .vsync_len      = 10,
 520                 .sync           = FB_SYNC_EXT,
 521                 .vmode          = FB_VMODE_NONINTERLACED
 522 } }, {
 523         .bus    = 2,
 524         .addr   = 0x38,
 525         .pixfmt = IPU_PIX_FMT_LVDS666,
 526         .detect = detect_i2c,
 527         .enable = enable_lvds,
 528         .mode   = {
 529                 .name           = "wsvga-lvds",
 530                 .refresh        = 60,
 531                 .xres           = 1024,
 532                 .yres           = 600,
 533                 .pixclock       = 15385,
 534                 .left_margin    = 220,
 535                 .right_margin   = 40,
 536                 .upper_margin   = 21,
 537                 .lower_margin   = 7,
 538                 .hsync_len      = 60,
 539                 .vsync_len      = 10,
 540                 .sync           = FB_SYNC_EXT,
 541                 .vmode          = FB_VMODE_NONINTERLACED
 542 } }, {
 543         .bus    = 2,
 544         .addr   = 0x48,
 545         .pixfmt = IPU_PIX_FMT_RGB666,
 546         .detect = detect_i2c,
 547         .enable = enable_rgb,
 548         .mode   = {
 549                 .name           = "wvga-rgb",
 550                 .refresh        = 57,
 551                 .xres           = 800,
 552                 .yres           = 480,
 553                 .pixclock       = 37037,
 554                 .left_margin    = 40,
 555                 .right_margin   = 60,
 556                 .upper_margin   = 10,
 557                 .lower_margin   = 10,
 558                 .hsync_len      = 20,
 559                 .vsync_len      = 10,
 560                 .sync           = 0,
 561                 .vmode          = FB_VMODE_NONINTERLACED
 562 } } };
 563
 564 int board_video_skip(void)
 565 {
 566         int i;
 567         int ret;
 568         char const *panel = getenv("panel");
 569         if (!panel) {
 570                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 571                         struct display_info_t const *dev = displays+i;
 572                         if (dev->detect(dev)) {
 573                                 panel = dev->mode.name;
 574                                 printf("auto-detected panel %s\n", panel);
 575                                 break;
 576                         }
 577                 }
 578                 if (!panel) {
 579                         panel = displays[0].mode.name;
 580                         printf("No panel detected: default to %s\n", panel);
 581                 }
 582         } else {
 583                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 584                         if (!strcmp(panel, displays[i].mode.name))
 585                                 break;
 586                 }
 587         }
 588         if (i < ARRAY_SIZE(displays)) {
 589                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 590                                     displays[i].pixfmt);
 591                 if (!ret) {
 592                         displays[i].enable(displays+i);
 593                         printf("Display: %s (%ux%u)\n",
 594                                displays[i].mode.name,
 595                                displays[i].mode.xres,
 596                                displays[i].mode.yres);
 597                 } else
 598                         printf("LCD %s cannot be configured: %d\n",
 599                                displays[i].mode.name, ret);
 600         } else {
 601                 printf("unsupported panel %s\n", panel);
 602                 ret = -EINVAL;
 603         }
 604         return (0 != ret);
 605 }
 606
 607 static void setup_display(void)
 608 {
 609         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 610         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 611         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 612         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 613
 614         int reg;
 615
 616         /* Turn on LDB0,IPU,IPU DI0 clocks */
 617         reg = __raw_readl(&mxc_ccm->CCGR3);
 618         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
 619                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
 620         writel(reg, &mxc_ccm->CCGR3);
 621
 622         /* Turn on HDMI PHY clock */
 623         reg = __raw_readl(&mxc_ccm->CCGR2);
 624         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
 625                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 626         writel(reg, &mxc_ccm->CCGR2);
 627
 628         /* clear HDMI PHY reset */
 629         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 630
 631         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 632         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 633         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
 634
 635         /* set LDB0, LDB1 clk select to 011/011 */
 636         reg = readl(&mxc_ccm->cs2cdr);
 637         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 638                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 639         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 640               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 641         writel(reg, &mxc_ccm->cs2cdr);
 642
 643         reg = readl(&mxc_ccm->cscmr2);
 644         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 645         writel(reg, &mxc_ccm->cscmr2);
 646
 647         reg = readl(&mxc_ccm->chsccdr);
 648         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
 649                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
 650                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 651         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 652                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 653               |(CHSCCDR_PODF_DIVIDE_BY_3
 654                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 655               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 656                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 657         writel(reg, &mxc_ccm->chsccdr);
 658
 659         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 660              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 661              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 662              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 663              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 664              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 665              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 666              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 667              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 668         writel(reg, &iomux->gpr[2]);
 669
 670         reg = readl(&iomux->gpr[3]);
 671         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 672             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 673                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 674         writel(reg, &iomux->gpr[3]);
 675
 676         /* backlights off until needed */
 677         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 678                                          ARRAY_SIZE(backlight_pads));
 679         gpio_direction_input(LVDS_BACKLIGHT_GP);
 680         gpio_direction_input(RGB_BACKLIGHT_GP);
 681 }
 682 #endif
 683
 684 int board_early_init_f(void)
 685 {
 686         setup_iomux_uart();
 687         setup_buttons();
 688
 689 #if defined(CONFIG_VIDEO_IPUV3)
 690         setup_display();
 691 #endif
 692         return 0;
 693 }
 694
 695 /*
 696  * Do not overwrite the console
 697  * Use always serial for U-Boot console
 698  */
 699 int overwrite_console(void)
 700 {
 701         return 1;
 702 }
 703
 704 int board_init(void)
 705 {
 706         /* address of boot parameters */
 707         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 708
 709 #ifdef CONFIG_MXC_SPI
 710         setup_spi();
 711 #endif
 712         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 713         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 714         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 715
 716 #ifdef CONFIG_CMD_SATA
 717         setup_sata();
 718 #endif
 719
 720         return 0;
 721 }
 722
 723 int checkboard(void)
 724 {
 725         puts("Board: MX6Q-Sabre Lite\n");
 726
 727         return 0;
 728 }
 729
 730 struct button_key {
 731         char const      *name;
 732         unsigned        gpnum;
 733         char            ident;
 734 };
 735
 736 static struct button_key const buttons[] = {
 737         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 738         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 739         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 740         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 741         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 742         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 743 };
 744
 745 /*
 746  * generate a null-terminated string containing the buttons pressed
 747  * returns number of keys pressed
 748  */
 749 static int read_keys(char *buf)
 750 {
 751         int i, numpressed = 0;
 752         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 753                 if (!gpio_get_value(buttons[i].gpnum))
 754                         buf[numpressed++] = buttons[i].ident;
 755         }
 756         buf[numpressed] = '\0';
 757         return numpressed;
 758 }
 759
 760 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 761 {
 762         char envvalue[ARRAY_SIZE(buttons)+1];
 763         int numpressed = read_keys(envvalue);
 764         setenv("keybd", envvalue);
 765         return numpressed == 0;
 766 }
 767
 768 U_BOOT_CMD(
 769         kbd, 1, 1, do_kbd,
 770         "Tests for keypresses, sets 'keybd' environment variable",
 771         "Returns 0 (true) to shell if key is pressed."
 772 );
 773
 774 #ifdef CONFIG_PREBOOT
 775 static char const kbd_magic_prefix[] = "key_magic";
 776 static char const kbd_command_prefix[] = "key_cmd";
 777
 778 static void preboot_keys(void)
 779 {
 780         int numpressed;
 781         char keypress[ARRAY_SIZE(buttons)+1];
 782         numpressed = read_keys(keypress);
 783         if (numpressed) {
 784                 char *kbd_magic_keys = getenv("magic_keys");
 785                 char *suffix;
 786                 /*
 787                  * loop over all magic keys
 788                  */
 789                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 790                         char *keys;
 791                         char magic[sizeof(kbd_magic_prefix) + 1];
 792                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 793                         keys = getenv(magic);
 794                         if (keys) {
 795                                 if (!strcmp(keys, keypress))
 796                                         break;
 797                         }
 798                 }
 799                 if (*suffix) {
 800                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 801                         char *cmd;
 802                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 803                         cmd = getenv(cmd_name);
 804                         if (cmd) {
 805                                 setenv("preboot", cmd);
 806                                 return;
 807                         }
 808                 }
 809         }
 810 }
 811 #endif
 812
 813 #ifdef CONFIG_CMD_BMODE
 814 static const struct boot_mode board_boot_modes[] = {
 815         /* 4 bit bus width */
 816         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 817         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 818         {NULL,          0},
 819 };
 820 #endif
 821
 822 int misc_init_r(void)
 823 {
 824 #ifdef CONFIG_PREBOOT
 825         preboot_keys();
 826 #endif
 827
 828 #ifdef CONFIG_CMD_BMODE
 829         add_board_boot_modes(board_boot_modes);
 830 #endif
 831         return 0;
 832 }